Agnisys.com

DVCon Europe Needs Automatic Register Verification and Generation

October 30, 2014 Antonio F Mondragon Comments Off

I feel like a bumblebee, going from the DVCon in US, to the next one in India to then to Europe. All this cross-pollination is exciting and enriching when experiencing

Getting Ready for DVCon India 2014

September 24, 2014 Antonio F Mondragon Comments Off

It is penultimate day – the day before the big event!

Preparing and launching the first ever DVCon India event feels like taxiing a plane down the runway, ready to take

9 Ways Commercial Register Generation Tools Provide Greater Value Than Custom Scripts

July 17, 2014 Uttam Sarkar Comments Off

Register Generation Tools Provide Great Value

The ebb and flow of the EDA industry shifts where a semiconductor company would use commercial tools for each task

The 5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

July 17, 2014 Antonio F Mondragon Comments Off

Modern SoCs get more and more complicated each and every day. As the complexity of modern electronic semiconductor device design increases, niche tools for every nook and cranny of the

DAC Day 2: System On Chip Design Challenges Addressed by Agnisys

June 4, 2014 Antonio F Mondragon Comments Off

System on Chip Design Challenges - The Highlight of DAC Day 2

It was a very busy day for Agnisys on the second day of the Design Automation Conference. On day

DVCon Europe Needs Automatic Register Verification and Generation

Getting Ready for DVCon India 2014

It is penultimate day – the day before the big event!

9 Ways Commercial Register Generation Tools Provide Greater Value Than Custom Scripts

Register Generation Tools Provide Great Value

The 5 Ways Register Generation Tools Reduce SV/UVM Implementation Time

DAC Day 2: System On Chip Design Challenges Addressed by Agnisys

System on Chip Design Challenges - The Highlight of DAC Day 2

EDA Companies must Collaborate or Die

Using IVerifySpec to test IDesignSpec: A case of doctor eating his own medicine!

IDesignSpec Provides Complete Register Design Automation

Agnisys makes Design Verification process extremely efficient!

Customer’s Music and DVCon 2012

UVM registers | Agnisys - Part 2

It is penultimate day – the day before the big event!

Register Generation Tools Provide Great Value

System on Chip Design Challenges - The Highlight of DAC Day 2