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UVM | Agnisys

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  • Posts Tagged "UVM"

An Update on Functional Safety and ISO 26262

October 29, 2021 Uttam Sarkar 0

Just about a year ago, I published a blog post about the emerging need for better functional safety and security in a wide range of electronic products. We recently

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System-Level Register and Sequence Verification with UVM and Embedded C/C++

September 23, 2021 Uttam Sarkar 0

As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate the SystemVerilog RTL design, Universal Verification Methodology (UVM) testbench models

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Specification Automation for Formal Verification

August 14, 2021 Uttam Sarkar 0

I hope that you’ve been able to attend or watch the recordings of the sessions in our latest webinar series on specification automation. We’re focusing on the requirements for

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Why Users Care about EDA Partnerships

January 26, 2021 Uttam Sarkar 0

Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular. When I thought about writing a blog post on this

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A Unified Development Flow for Embedded Systems

December 11, 2020 Uttam Sarkar 0

When engineers discuss system-on-chip (SoC) designs, they’re almost always talking about embedded systems with both hardware and software content. In fact, many argue that a chip must contain at least

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A Unified Flow for Embedded Systems Development

October 28, 2020 Uttam Sarkar 0

Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual

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Specification-Driven UVM Testbench Generation

September 22, 2020 Uttam Sarkar 0

In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world

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Three Steps to Set Up a RISC-V SoC UVM Testbench

June 17, 2020 Uttam Sarkar 1

Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides

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Automation of the UVM Register Abstraction Layer

May 28, 2020 Uttam Sarkar 0

A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the

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Adopting New Methods For Faster Development Of RISC-V based SoCs

December 9, 2019 marketing@agnisys.com 0

The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course, the various technologies for the automotive industry has led to

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