As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate the SystemVerilog RTL design, Universal Verification Methodology (UVM) testbench models
Read moreIn my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators
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By Louie de Luna, Agnisys Director of Sales and Marketing UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics industry. Since
Read moreIn our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If we take a look at the AMBA®AXI4Lite bus protocol, it
Read moreOverheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher levels of productivity. I find that interesting as we at
Read moreHere we go! The Design and Verification Conference (DVCON 2014) is round the corner. Make sure you register for the event which has been one of the premier
Read moreWe almost didn’t go to DAC this year, and that would have been a big mistake. Monday started out with one of our biggest competitor dropping by to say hello
Read moreWe had a great first day at DAC. All the talk about recession and economic doom were hard to believe. People were enthusiastic and upbeat. Even the guys and gals
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