Machine Learning (ML) is a powerful concept where the trainable engine and a dataset can be made to predict future outputs. This concept has been leveraged to help users create IP and SoC specification. The ML algorithms have been embedded in software that is not visible to the end user, which makes the creation of the register specification a simple and less erroneous task. Having defined the specification, one can automatically create design code
and verification environment. We present a novel way to capture design intent vis-à-vis addressable registers and sequences, use ML algorithms to identify patterns in the natural language description and to automate the whole design and the verification environment from it. We also present our experience in converting System Verilog Assertions into plain English language using ML algorithms.

Please fill the form to download the slide presentation on Machine Learning in Register Automation and Verification.