As we close in on the final days of 2021, I can’t help but think back over the events of the year and offer a few observations. At the front of my mind is the recent Design Automation Conference (DAC) in San Francisco. It was at an unusual time—December rather than June or July—and it was certainly not back to the full-scale show we all remember from the past. Some exhibitors pulled out due to pandemic-driven travel restrictions, and staffing at some booths was lower than usual. Nevertheless, it was still a very good show for Agnisys. It was great to see users in person again and to discuss their latest chip design and verification challenges.
It was also nice to be able to show them our latest tools and technologies, especially since we had a lot new to talk about. As I mentioned in my DAC preview post, we made two major announcements leading up to the show. The first was the release of IDS-FPGA, part of our IDesignSpec™ (IDS) family. IDS-FPGA is integrated with the Xilinx Vivado and Intel Quartus Prime software suites to make it easier to use our automated code and IP generators on FPGA projects. As we expected, we saw considerable interest in this new offering and enjoyed the chance to demonstrate it at our booth.
We saw even more interest in our AI/ML-powered iSpec.ai technology, which converts English statements of design intent into SystemVerilog Assertions (SVA), and vice versa. We were happy to demonstrate this as well, but we encouraged visitors to try it themselves on our www.ispec.ai crowdsourcing site. For encouragement, we held a content each day in which users could use this site to help answer questions on an SVA quiz and try to win an SoC Development Board or a 30000mAh Power Bank. It was a lot of fun, and we had some very happy users.
Another positive aspect of DAC this year was its co-location with the RISC-V Summit. As you probably know, the RISC-V processor is one of the hottest topics in electronics right now, so it made sense for the exhibits to be combined with DAC and for the technical sessions to be held in parallel. I was proud to present a talk on “A System Level Verification and Validation Environment using SweRV” that promoted some good questions from the audience. I hope that these two events can be held together in future years as well.
The week after DAC, the Design and Verification Conference (DVCon) India was also an in-person show. Agnisys presented a paper on “IP Generators: A Better Reuse Methodology” and “Smart IP Integration and SOC Assembly” in the poster session. DVCon Europe and the original DVCon in the U.S. were both virtual this year, and of course we participated in these events as well. As I’ve noted before, the virtual booth concept just doesn’t seem to have the same appeal as a physical exhibit hall but at least it provides additional chances to connect with our users.
Another highlight of 2021 was the first Agnisys User Group Educational Roundtable (AUGER), a lively virtual event that worked much better than online trade shows because of its strong technical content. Our engineering team presented sessions on our latest tools and features, the many user customizations available, the quality checks that we perform on register maps, and the process for ensuring functional safety and security in chip designs. We also had an excellent user presentation and a roundtable feedback session. We will definitely have an AUGER again in 2022.
The more I think about it, the more I realize that this was a very busy and successful year. We offered a series of 7 webinars that are available for replay on demand, and we published nearly 20 blog posts and technical articles. You can find pointers to all of these on our website. I have no doubt that the next year will be equally busy and successful, and I eagerly anticipate engaging with all of you. I wish you the best during this holiday season, I deeply hope that you remain healthy, and I look forward to a happy and prosperous 2022 for us all.