IDesignSpec™

IDesignSpec™ enables IP, SoC, and FPGA teams to standardize on your register specification and generate Verilog, VHDL, UVM, C headers, Word, Excel, PDF, and many other formats from it. IDesignSpec is currently available as a plug-in to Word and, Excel, and as a batch utility.

IDS NextGen™

IDS NextGen™ is the next generation product which builds upon the award-winning register tool IDesignSpec™. With IDS-NG teams can capture the register and sequence specification for IPs and SoCs. It is a cross platform enterprise class product that is an indispensable tool for design, verification, software, firmware and technical documentation teams. It is the only tool in the world that can automatically convert natural language into code.

Specta-AV™ 

Specta-AV™ is a comprehensive UVM testbench generator that automates verification of complete IP having addressable registers and user application logic with complex sequences, checks and coverage models

ARV™ 

ARV™ is an add-on to IDesignSpec™ that creates a complete verification environment for automatically verifying all addressable registers with all access types and all complex types for IP and SoC designs. It is a tool that saves you verification resources.

ISequenceSpec™

ISequenceSpec™ creates portable register- based sequences and generates UVM and firmware sequences from your specification. It uses the register information by importing standard formats such as IP-XACT, SystemRDL, and any IDS format.

SLIP-G™ 

SLIP-G^TM is a configurable IP generator which is capable of generating certain standard IPs, like, GPIO, TIMER, I2C, and PIC. These IPs are designed to be easily customizable and configurable to meet any SoC requirements. SLIP-G ^TM is also capable of creating their configuration APIs, which are a set of initialization sequences to initialize the user controlled registers of the standard IPs through simple arguments. These configuration APIs  can be used to set up a desired mode of operation for the created IPs. Furthermore, these IPs are fully verified and validated. User can easily configure and customize them, as required.

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SoC Enterprise™ 

SoC Enterprise^TM provides a flexible and feature rich tool for comprehensive SoC design assembly. It’s more than an assembler as it can also generate RTL plumbing components like bus-aggregators, bridges, and multiplexers. It leverages the already existing and mature register solution IDesignSpec^TM along with the new “Standard Library of customizable & configurable IP
Generators” (SLIP-G^TM)

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DVinsight™ 

DVinsight™ is a smart editor for creating UVM based System Verilog Design and Verification code is now available on Redhat 7, 6 & 5, Ubuntu and Windows. Simplify your SV/UVM coding process with this new editor which you can use for free.