| Date/Time | Event |
|---|---|
|
03/18/2021 11:00 am - 3:00 pm |
AUGER 2021 - Agnisys User Group Educational Roundtable |
|
03/01/2021 - 03/03/2021 12:00 am |
DVCon U.S. 2021 - Virtual |
|
12/17/2020 3:00 pm - 4:00 pm |
Webinar on System Development Using Agnisys |
|
12/08/2020 - 12/10/2020 9:00 am - 5:00 pm |
RISC-V SUMMIT 2020 Virtual |
|
07/20/2020 - 07/23/2020 10:30 am - 1:30 pm |
Design Automation Conference (DAC) 2020 |
|
06/18/2020 10:00 am - 11:00 am |
Webinar on Understanding clock domain crossings |
|
06/11/2020 10:00 am - 11:00 am |
Webinar on AI based sequence detection for verification and validation of IP/SoCs |
|
06/04/2020 10:00 am - 11:00 am |
Webinar recording on Automatic verification using Specta-AV – a boost to verification productivity |
|
05/28/2020 10:00 am - 11:00 am |
Webinar recording on Steps to setup RISC-V based SOC Verification Environment |
|
05/21/2020 10:00 am - 11:00 am |
Webinar recording on A flexible and customizable flow for IP connectivity and SoC design assembly |
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