UPCOMING EVENTS
Webinar
Accelerating FPGA Development: From Specification to System Validation with IDS-FPGA
Join us for an insightful webinar where Agnisys will showcase IDS-FPGA, a comprehensive solution designed to automate and accelerate the FPGA development process.
The session will feature a complete design flow demonstration using an Ethernet Generator and Monitor example. The flow begins with IDS-NG, our GUI-based tool, which is used to define the design and generate the RTL. Next, IDS-Integrate is employed to automatically generate mirror files and connection ports required for system integration.
In the following step, TCL scripts are generated within the IDS directory to incorporate these files into the overall design. The process continues with design verification and validation using IDS-Verify and IDS-Validate, which generate UVM and C-based tests and assertions, ensuring design correctness and completeness.
The C tests are then executed within the software environment, enabling full hardware/software co-design and co-verification
June 22-25, 2025
DAC 2025
We are excited to announce that we will be exhibiting at DAC 2025 at Booth #2622! As a leader in Design, Verification & Integration automation, we are revolutionizing the way AI chip companies develop hardware. Our innovative solutions empower AI and semiconductor companies to accelerate chip design, enhance verification efficiency, and ensure first-pass success. From AI-driven automation to seamless hardware/software co-design, Agnisys is helping engineers push the boundaries of AI innovation. Visit us at DAC 2025 to see how our technology is shaping the future of AI chip design!
September 9, 2025
DVCon Taiwan 2025
Agnisys will be showcasing at the Design and Verification Conference in Taiwan, this will be held on 9th September 2025 as an In-Person. Now in its third year, DVCon Taiwan 2025 continues its mission to bring together the local and international community to exchange ideas, explore the latest methodologies, and discuss emerging trends in design and verification.
September 10-11, 2025
DVCon India 2025
Agnisys will be showcasing at the Design and Verification Conference in India, this will be held on 10-11th September 2025 as an In-Person conference. The conference will follow the contemporary Indian version of a two-day conference with in-depth technical content spread across both days. This 10th conference will be the pinnacle of innovation, collaboration and insight.
Older Events
Webinar in Japan, Korea & China
Fastest SoC front-end design using Agnisys (Part 2)
Integrating thousands of IP blocks in a System-on-Chip (SoC) design manually is both time-intensive and prone to errors. Writing RTL to define these connections demands substantial effort, making it difficult to efficiently manage and scale complex designs.
Agnisys addresses this challenge with IDS-Integrate—a robust automation tool that streamlines IP integration by automatically establishing connections based on predefined APIs. With support for TCL and Python-based APIs, IDS-Integrate enables efficient and flexible IP connectivity, significantly reducing development time. The tool also auto-generates RTL and IP-XACT outputs, eliminating manual coding tasks and ensuring consistency across the design.
This upcoming webinar will showcase how IDS-Integrate enhances design productivity by automating IP integration. Key features such as hierarchy manipulation, automated connectivity, and TGI (Tight Generator Interface) access will be explored. Attendees will gain valuable insights into how IDS-Integrate simplifies complex SoC design workflows and ensures reliable, efficient IP connectivity.
Webinar in Japan, Korea & China
Fastest SoC front-end design using Agnisys (Part 1)
Manually connecting thousands of IPs in an SoC design is a time-consuming and error-prone process. Writing RTL to establish these connections requires significant effort, making it challenging to manage complex designs efficiently.
Agnisys offers a powerful solution to automate this process with IDS-Integrate, a tool that simplifies IP integration by automatically connecting various IPs based on predefined API. IDS-Integrate provides a TCL and Python-based API, enabling IP connectivity while significantly reducing design time. The tool also generates RTL and IP-XACT outputs, eliminating the need for manual coding and ensuring consistency across designs.
This webinar will demonstrate how Agnisys IDS-Integrate automates IP integration, saving time and improving accuracy. We will explore key features such as hierarchy manipulation, automatic connectivity, and TGI (Tight Generator Interface) access. Attendees will gain insights into how IDS-Integrate streamlines complex SoC design flows and ensures efficient connectivity between IP blocks.
Webinar in Japan, Korea & China
AI Chip Design Using Agnisys
The design of AI chips is centered around optimizing performance for computationally intensive operations like Multiply-Accumulate (MAC), which is fundamental to neural network workloads. To achieve the required speed and energy efficiency, modern AI chip architectures integrate advanced techniques such as systolic arrays, parallel processing, and domain-specific accelerators.
Agnisys plays a crucial role in this ecosystem by automating key aspects of chip design and verification. Tools like IDesignSpec (IDS) streamline the generation of RTL for registers and memories, ensuring compliance with multiple bus standards while minimizing errors and expediting development. Additionally, Agnisys solutions leverage AI-driven automation to enhance design verification, reducing manual effort and improving overall accuracy.
This webinar will explore how Agnisys supports cutting-edge AI chip architectures, including neuromorphic computing, 3D stacking, and edge-optimized processors for applications in IoT, robotics, and beyond. By integrating AI within the design process and enabling next-generation AI hardware, Agnisys helps engineers push the boundaries of computational efficiency, precision, and innovation.
February 24-27, 2025
DVCon U.S.
Efficient register and memory map management is vital for today’s complex System-on-Chip (SoC) designs. In this webinar, discover how Agnisys’s IDesignSpec Suite leverages SystemRDL to automate design, verification, and integration processes. Learn best practices, explore real-world use cases, and see how IDesignSpec enhances efficiency, reduces errors, and ensures compliance with industry standards, transforming your SoC development workflow.
Don’t miss this opportunity to see how Agnisys’s IDesignSpec Suite can revolutionize your SoC development with the power of SystemRDL!”
Webinar
AI Chip Design Using Agnisys
The design of AI chips hinges on optimizing performance for computationally heavy operations like Multiply-Accumulate (MAC), a core component of neural network workloads.
To meet the demands of speed and energy efficiency, AI chip architectures increasingly integrate advanced techniques like systolic arrays, parallel processing, and domain-specific accelerators. Agnisys tools contribute significantly to this ecosystem by automating key steps in chip design and verification.
For instance, IDesignSpec (IDS) enables efficient generation of RTL for registers and memories while supporting multiple bus standards. These capabilities streamline the transition from specification to implementation, minimizing errors and accelerating time-to-market. With a suite that leverages neuromorphic chips, 3D stacking, and edge-specific processors to address emerging AI use cases like IoT and robotics.
Together, these advancements push the boundaries of AI computing while maintaining a focus on precision, reliability, and innovation.
Webinar
Optimizing Hardware Design with SystemRDL: Tools, Techniques, and Tips
Efficient register and memory map management is vital for today’s complex System-on-Chip (SoC) designs. In this webinar, discover how Agnisys’s IDesignSpec Suite leverages SystemRDL to automate design, verification, and integration processes. Learn best practices, explore real-world use cases, and see how IDesignSpec enhances efficiency, reduces errors, and ensures compliance with industry standards, transforming your SoC development workflow.
Don’t miss this opportunity to see how Agnisys’s IDesignSpec Suite can revolutionize your SoC development with the power of SystemRDL!”
Webinar
Advantages of using IP-XACT and TGI for SoC Development
SoC development involves managing registers, integrating IPs, and ensuring collaboration across teams, often leading to iterative rework. IP-XACT, an IEEE standard by Accellera, streamlines workflows by standardizing data exchange and enabling automation. The latest IP-XACT 2022, with its TGI API, simplifies design processes, enhances efficiency, and reduces development cycles. This webinar will demonstrate how to leverage IP-XACT for optimized resources, seamless integration, and faster time-to-market.
August 29, 2024
DVCon Japan
The Design and Verification Conference is the premier conference on the application of languages, tools, methodologies and standards for the design and verification of electronic systems and integrated circuits. Agnisys, the pioneer and industry leader in Golden Executable Specification Solutions™ will be presenting a paper at DVCon Japan titled, “Auto Gen of Embedded System Layer using PSS and System RDL” in Room 3 from 14:15 to 14:45. Learn how our certified IDesignSpec™ Solution Suite leverages a golden executable specification to capture and centralize registers, sequences, and connectivity for Intellectual Property (IP) and System-on-a-Chip (SoC) projects. We help market makers accelerate their front-end SoC, FPGA, and IP development – let us help you ensure your project success!
September 18-19, 2024
DVCon India
Agnisys will be showcasing at the Design and Verification Conference in India, this will be held on 18-19th September 2024 as an In-Person conference. The conference will follow the contemporary Indian version of a two-day conference with in-depth technical content spread across both days. This 9th conference will be the pinnacle of innovation, collaboration and insight.
March 4-7, 2024
DVCon US
The Design & verification conference and Exhibition is the premier conference on the application of languages, tools and methodologies and standards for the design and verification of electric systems and integrated circuits.
Visit with Agnisys, the Industry Leader in Golden Executable Specification Solutions™, in booth #103.
Agnisys automates design, verification, and validation by capturing and centralizing registers, sequences, and connectivity for your IP and SoC development projects. Our solutions team can show you how to leverage IP-XACT, PSS, SystemRDL, YAML, Word, and Excel templates to dramatically increase productivity and reduce risk.
June 23-27, 2024
DAC 2024
Agnisys is excited to participate in the 61st Design Automation Conference (DAC) 2024, taking place from June 23 to 27, at the Moscone West in San Francisco, CA.
At Booth #2457, we will showcase our latest automation solutions designed to enhance the efficiency and performance of complex hardware systems. We are also proud to sponsor
the “I LOVE DAC” program, offering 44 Engineering Track promo codes on a first-come, first-served basis. Additionally, Agnisys will present at the Exhibitor Forum on “Object Oriented Embedded Hardware for Operational Excellence.” Join us to explore innovative methodologies in embedded hardware design, engage with our experts, and benefit from valuable learning opportunities at DAC 2024. Participate in our design contest, you will discover how easy it is to use IDS-NG for creating digital designs.
April 25, 2024
IP SoC Silicon
Valley 24
Agnisys will participate in the IP-SoC Silicon Valley 24 organized by Design-and Reuse, where innovations will be discussed around IP and SoC solutions.. As a leading provider of innovative solutions for semiconductor design automation, Agnisys experts will present the latest in IP and SoC development.
Agnisys invites you to visit booth #15 at the IP-SoC Silicon Valley 24 to engage with its team of experts, explore live demonstrations, and discover firsthand how to develop IP/SoC faster, better, cheaper using its unique products. We will also present a talk about how we are able to achieve fastest development by “Automatic generation of Device Driver and Programmer’s Reference Manual from PSS”.
