Newsletter 2022 Q3 | Agnisys
September 13, 2022

Newsletter 2022 Q3 | Agnisys

Newsletter 2022 Q3 with a remarkable set of product updates.
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Newletter 2022 Q2
June 15, 2022

Newletter 2022 Q2

Agnisys Newsletter Q2 2022
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Newsletter 2022 Q1 | Agnisys
December 31, 2021

Newsletter 2022 Q1 | Agnisys

Agnisys newsletter Q4 2021 - New capabilities in the IDesignSpec family of products
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Newsletter 2021 Q3 | Agnisys
September 30, 2021

Newsletter 2021 Q3 | Agnisys

Various new significant enhancements have been introduced recently in products
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Newsletter 2021 Q2 | Agnisys
June 26, 2021

Newsletter 2021 Q2 | Agnisys

Significant new enhancements to IDS are Multicast/Broadcast Address Decoder, parameterization update of...
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Newsletter 2021 Q1 | Agnisys
April 6, 2021

Newsletter 2021 Q1 | Agnisys

A significant new enhancement to IDS has been the introduction of SRAM based register implementation.
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Newsletter 2020 Q4 | Agnisys
December 31, 2020

Newsletter 2020 Q4 | Agnisys

New product enhancements include Parametrization using SystemRDL, Functional Safety, and Security.
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Newsletter 2020 Q3 | Agnisys
October 8, 2020

Newsletter 2020 Q3 | Agnisys

A significant new enhancement to IDS has been chip-in-chip, now the chip can be a container for other chip...
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Newsletter 2020 Q2 | Agnisys
July 14, 2020

Newsletter 2020 Q2 | Agnisys

The basic differences between Paged registers and Alternate register, Auto-Mirroring for volatile registers,...
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Newsletter 2019 Q4 | Agnisys
December 9, 2019

Newsletter 2019 Q4 | Agnisys

This will focus on Board Prototyping, Field Error Signals, Traceability in IDesignSpec and Verification...
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Newsletter 2019 Q3 | Agnisys
August 5, 2019

Newsletter 2019 Q3 | Agnisys

In this newsletter, you will find thoughts and insights about SystemRDL loopholes, security design strategies...
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Newsletter 2019 Q2 | Agnisys
April 12, 2019

Newsletter 2019 Q2 | Agnisys

In this newsletter, you will find articles about the basic differences between SystemRDL, YAML & RALF,...
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Newsletter 2019 Q1 | Agnisys
January 14, 2019

Newsletter 2019 Q1 | Agnisys

In this newsletter, you will find articles about the basic differences between IP-XACT and SystemRDL, best...
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DVCon Europe Special Edition – Agnisys Spotlight 2018 | Agnisys
October 12, 2018

DVCon Europe Special Edition – Agnisys Spotlight 2018 | Agnisys

With DVCon Europe 2018 just around the corner, this special edition of the Agnisys Newsletter focuses its...
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DAC Special Edition – Agnisys Spotlight 2018 | Agnisys
June 25, 2018

DAC Special Edition – Agnisys Spotlight 2018 | Agnisys

A lot is happening at Agnisys this quarter. We are delighted to introduce this DAC Special Edition of the...
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DVCon US 2018 Special Edition | Agnisys
February 22, 2018

DVCon US 2018 Special Edition | Agnisys

With DVCon 2018 just around the corner, this special edition of the Agnisys Newsletter focuses its spotlight...
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Spotlight – 2017 Dec | Agnisys
December 28, 2017

Spotlight – 2017 Dec | Agnisys

Agnisys has created a new Integrated Development Environment (IDE) – IDS NextGen, which enables users to...
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Spotlight – 2017 Oct | Agnisys
October 16, 2017

Spotlight – 2017 Oct | Agnisys

The input format of Duolog is now supported by IDesignSpec with outputs including Verilog, UVM, CHeader, and...
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Spotlight – 2017 June | Agnisys
June 1, 2017

Spotlight – 2017 June | Agnisys

Special FIFO Register - Bigger reg width registers in IDesignSpec - and more
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Spotlight – 2017 Feb | Agnisys
February 24, 2017

Spotlight – 2017 Feb | Agnisys

IP-XACT is an industry standard IEEE 1685-2009/2014 which is recognized by the electronics community as the...
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Spotlight – 2016 Nov | Agnisys
November 21, 2016

Spotlight – 2016 Nov | Agnisys

many product updates in this newsletter.
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Spotlight- 2016 Aug | Agnisys
August 17, 2016

Spotlight- 2016 Aug | Agnisys

In this issue we bring you examples and case studies about how system development teams – hardware...
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