Setting a High Standard for Standards-Based IP
In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has proven to be quite popular with our users, and that’s not
Read moreAutomating the UVM Register Abstraction Layer (RAL)
It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a
Read moreAutomating IP and SoC Development
The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed in my last post, we held our first Agnisys
Read moreAUGER: Celebrating Our Users
In my last post, I discussed the importance of partners to the EDA industry in general, and to Agnisys in particular. Partnerships exist because our users demand them. In today’s
Read moreWhy Users Care about EDA Partnerships
Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular. When I thought about writing a blog post on this
Read moreA Unified Development Flow for Embedded Systems
When engineers discuss system-on-chip (SoC) designs, they’re almost always talking about embedded systems with both hardware and software content. In fact, many argue that a chip must contain at least
Read moreFunctional Safety and Security in Embedded Systems
Electronics in general, and embedded systems in particular, become more critical every day. There is hardly a single aspect of our lives that is not controlled, monitored, or connected by
Read moreA Unified Flow for Embedded Systems Development
Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual
Read moreAutomatic Handling of Register Clock Domain Crossings
Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and verification. Today’s designers operate very differently than their predecessors who
Read moreSpecification-Driven UVM Testbench Generation
In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world
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