The UVM register model is an essential component of the UVM based verification…

In engineering, we often go about our work not knowing how that work…

We all have different tastes, different habits and when it comes to work…

After almost a decade of focusing on SV, UVM, SystemC to build software…

Hardware is verified using simulators. Software compiled and debugged using compilers and debuggers.…

The Design Automation Conference is over for the year. Attendee leads or inquiries,…

Whether dealing with SoCs or a disaster in space, determining the correct set…

While more registers means more functionality and configurability, more is not always better.…

Important observations from Einstein and New England’s ice traders.. Albert Einstein defined it…

Identifying the challenges in moving from a static spec to a live one.…

The DVCon Conference this year, was quite eventful for us with a lots…

Wow what a marvelous year 2015 has been to Agnisys, with full of…

The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but…

 Somewhere in the deep trenches of a UVM based verification project, an engineer…

Using Mentor QVIP to prove IDesignSpec™ generated IP’s compliance In our domain, we automatically…

Moore’s law prediction about the increase in density of an SoC design continues…

Electronic Design Automation Trade Show Update – 52DAC Overheard a lot of talk…

With the Design Automation Conference wrapping up this week in San Francisco, there…

We talk about creation of complex registers in IDesignSpec, generation of their suitable…

Agnisys just released DVinsight-Pro version 2.0 with many new features that enable much…

So we have been working in the register specification space for a long…

The Large Hadron Collider (LHC) at CERN is the worlds largest and most…

I feel like a bumblebee, going from the DVCon in US, to the…

DVCon had a solid start in Bangaluru, India.  The audited attendee numbers will…

It is penultimate day – the day before the big event!  Preparing and…

Register Generation is a Must-Have Capability Today’s SoC designs contain several thousands of…

Register Generation Tools Provide Great Value The ebb and flow of the EDA…

Modern SoCs get more and more complicated each and every day.  As the…

Ending the last day of DAC strong with a presentation of DVinsight, a…

System on Chip Design Challenges – The Highlight of DAC Day 2 It…

The first day of the Design Automation Conference for Agnisys was exciting.  We…

As an EDA company our development cycle seems to revolve around DVCon and…

DVCon 2014 was a wrap. It was marked by record attendance and participation…

Here we go! The Design and Verification Conference (DVCON 2014) is round the…

Recently at the sidelines of DAC, Anupam Bakshi, CEO of Agnisys, Inc. sat…

IDesignSpec generates several outputs from a single spec. We started out as a…

by Pawan Fangaria Published on 05-19-2013 07:30 PM in Semiwiki It goes without…

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to…

OK rockets are not taking off yet, but we are excited to launch…

I admit it, I get a high when meeting customers and hearing how…

So the cat is out of the bag. We are working on an…

Its heartening to see greater cooperation between various EDA companies, both big and…

Hardware design verification consumes more than 60% of resources, often more than that.…

We almost didn’t go to DAC this year, and that would have been…

Started blogging again, this time from our own blogging site. Its DAC time…

We had a great first day at DAC. All the talk about recession…

I’m thrilled. Finally, we have a customer who sees the value that IDesignSpec…

Business schools teach us that the way to set the price on a…

As you know we have created a brand new EDA tool that saves…

I’m so excited … After years of work, my team and I have…