Taking the First Step in Portable Stimulus Adoption
As chips get ever larger and more complex, one thing is for certain: the electronic design automation (EDA) tools, techniques, and methodologies used to develop silicon become more sophisticated. Every stage of chip development—architecture, design, implementation, verification, programming, validation, and test—consumes more time and resources. Continual improvement in EDA is the only way to avoid total project meltdown. This situation puts enormous pressure on Agnisys and other solutions providers to adopt the latest and greatest technologies to help our users succeed.
It's easy to check off a list of development improvements that have helped over the years: automated layout, register transfer level (RTL) design, logic synthesis, constrained-random testbenches, formal and static verification, automated test pattern generation (ATPG), and more. It seems that every few years a new technique, guided by a comprehensive methodology, emerges to tackle the ever-rising size and complexity of designs. In recent times, perhaps no new approach holds more promise than the portable stimulus standard (PSS) developed by Accellera.
What is Portable Stimulus?
Verification has been the dominant phase of chip development for some time; most projects consume about two-thirds of their resources ensuring that the design is correct. Virtually every project uses simulation as the main verification method, relying on testbenches, constrained-random stimulus generation, and coverage as defined by the Universal Verification Methodology (UVM). Having standard testbenches and models enables easier verification reuse across projects, both within a company and across companies via a robust industry in design IP and verification IP (VIP).
PSS was defined by Accellera as a way to specify verification intent without explicitly coding a UVM testbench, UVM tests, or C/C++ tests. The idea is to specify this intent in an abstract but precise way so that a portable stimulus EDA tool can generate the files needed for verification, embedded programming, pre-silicon validation, post-silicon validation, and perhaps even some aspects of production test. The generated tests run in simulation, emulation, FPGA prototypes, and actual fabricated chips in the bringup lab.
This is a powerful concept. Automatic generation of both UVM tests and C/C++ embedded code ensures that the hardware and software aspects of the design agree. This saves a great deal of time during the validation phases. But PSS goes beyond this “horizontal” reuse to enable “vertical” reuse as well. Tests can be generated for individual IP blocks, subsystems, complete chips, and even multi-chip systems. This is a major step beyond UVM, which does not provide much assistance for reusing lower-level tests at higher levels of the design hierarchy. With PSS, it happens at the push of a button.
Adoption of Portable Stimulus
PSS was based on a number of academic and commercial projects that used some form of verification intent capture and automated test generation. By standardizing the input format and codifying the methodology, portable stimulus has emerged as an important component in chip and IP development. There are many published success stories of projects that have successfully used PSS and portable stimulus tools to save time and engineering resources while improving test coverage. The value of PSS is clear, and not many would argue against its power and capabilities.
So why isn’t every project using PSS? The simple truth is that it requires a different way of thinking about verification and validation. Any industry veteran has seen that most major advancements in chip development have required a new viewpoint and taken time to catch on. For example, both logic synthesis and constrained-random testing were being used on advanced projects for years before they went mainstream. PSS is in such a phase now; despite its many successes there are still some users who don’t truly understand it and may be nervous about trying it.
EDA history has shown that the best way to encourage adoption of new technologies is to provide automated solutions for specific problems. Many PSS observers point to the industry experience with formal verification as a relevant example. The available of pushbutton formal solutions for such challenges as clock-domain crossings (CDCs), sequential equivalence checking, and connectivity verification enabled users to get started with minimal effort. Once they saw the power of formal firsthand, they began writing their own properties and assertions to gain even more value.
Register and Sequence Specification with PSS
PSS is benefiting from an evolutionary adoption similar to formal. Writing a PSS modelwith the complete verification intent for an IP or chip is easier if one starts by using PSS to solve a specific problem. The specification of the registers in a design, and the sequences needed to configure and test them, is an ideal place to start. The latest release of the standard has language constructs that make it very easy to specify register sets, registers, and the fields within them. Specifying sequences is also natural with PSS, since abstract test definition is squarely within its primary function.
With a PSS model of their registers and sequences, users of the Agnisys IDesignSpec™ Suite can automatically generate many diverse types of files used by different development teams. For verification and pre-silicon validation, they generate UVM register abstraction layer (RAL) models and UVM-based tests. These include both tests based on the register types and tests that use the sequences specified in the PSS model. For pre-silicon and post-silicon validation, IDesignSpec generates C/C++ tests that run on the embedded processors in the design.
The generated tests span all the way from high-level architectural simulations to real silicon in the bringup lab. But, as per the goals of PSS, they also span from IP blocks to the complete system. Users can run UVM simulations on the register blocks standalone and then run corresponding embedded tests on a multi-chip board in the lab. There’s no recoding required; the same PSS model is used to generate all the files for all the teams. This saves time and resources not just once, but every time that the register or sequence specification changes.
The power and value of PSS has been well proven, and more chip development teams are adopting it every day. Agnisys provides an excellent way to get started, by using PSS to specify registers and sequences, followed by automated test generation. PSS support complements all the other great features in IDesignSpec, such as generation of the register RTL design and customer-ready documentation. With Agnisys, adoption of portable stimulus is fast and easy. A demonstration or evaluation license is availableanytime, so don’t be shy!