The Agnisys IDesignSpec suite offers your product teams a closely linked set of products, including a unified graphical design interface (GDI) frontend and a unified generation engine. These can be shared across all teams to maximize efficiency and support fully automated flows.
The Methodology for Faster Development of Better Semiconductors
The specification to design quandary
Traditionally, there has been no automated link between design specifications and the development process. Designers hand-wrote RTL, embedded programmers manually wrote C/C++ code, and verification teams coded up testbenches and tests, all from the same specification. Natural language is inherently ambiguous, so different teams had different interpretations. Much of the project was spent fixing bugs due to inconsistencies.
Impact of specification changes
Specifications change many times over the course of a project, and every time this happened the development process was repeated. Changes had to be communicated to each team, which interpreted them and manually updated their code. New inconsistencies inevitably arose, resulting in more painful debugging to fix the problems. The cost in schedule time and project resources was enormous.
Executable specifications save time, reduce errors
In the Agnisys methodology, many specifications can be written in executable formats, from which Agnisys tools can automatically generate design, programming, verification, validation, and documentation files. Every time a specification changes, all files are automatically regenerated with the changes incorporated. This replaces tedious manual effort and keeps all your teams in sync at all times.
Semiconductor Industry Standards Enablement
Agnisys leverages industry standards in every aspect of its products. RTL designs are generated in Verilog, VHDL, and SystemC, and include interfaces for bus standards such as APB, AHB, AHB-Lite, AXI-Lite, AXI4, AXI4-Lite, TileLink, Avalon, and Wishbone. Generated standard IP blocks include AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPU, Timer, and UART.
Verification and validation files are generated in SystemVerilog compliant with the Universal Verification Methodology (UVM). Generated C/C++ code is fully standard compliant. Documentation is generated in HTML, PDF, Markdown, and DITA formats.
Other file formats supported include SystemRDL, IP-XACT, YAML, JSON, RALF, and CSV. Customization scripts can use standard Tcl, Python, and Velocity. In addition, the Agnisys IDesignSpec Suite has been certified as meeting the ISO 26262 and IEC 61508 safety standards.
How Agnisys Eliminates Redundancies in Semiconductor Design, Verification, and Validation
Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.
Agnisys IDesignSpec GDI automates the design and verification of all the memories, register sets, registers, and register fields in your design. You can choose from a variety of input formats or use the highly intuitive specialized editor contained in IDesignSpec GDI. This executable specification supports simple registers as well as many special register types such as indirect, indexed, read-only /write-only, alias, lock, shadow, FIFO, buffer, interrupt, counter, paged, virtual, external, and read/write pairs.
From the specifications, IDesignSpec GDI generates a complete RTL design description for the registers and memories, including a bus slave and decode logic specific to the user-selected bus protocol and any clock-domain-crossing (CDC) synchronization logic needed. IDesignSpec GDI also generates a SystemVerilog model compatible with the UVM standard, C/C++ headers for embedded programming, and high-quality documentation suitable for inclusion in user manuals.
Agnisys IDS-Batch CLI generates all the same files as IDesignSpec GDI, but in command-line mode. All other Agnisys products also generate their outputs in command-line mode using IDS-Batch CLI and support graphical entry and interactive generation with IDesignSpec GDI, which serves as a unified GUI.
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Agnisys IDS-Verify automatically generates a complete UVM-based verification environment for verifying all your addressable registers and memories for their access types and complex behavior. The generated testbench is fully compliant with UVM, and includes bus agents, monitors, drivers, adaptors, predictors, and sequences, as well as Makefiles for various standard simulators.
IDS-Verify generates test sequences for register fields, register-level sequences, positive/negative sequences for special registers behavior, and register accesses. It also allows you to specify and include your custom sequences in the flow. The built-in standard register and memory tests in UVM typically provides only ~60% coverage. IDS-Verify closes this gap by generating test sequences that provide ~100% coverage out-of-the box for your register and memory functionality.
IDS-Verify also generates SystemVerilog Assertions (SVA) that can be used in simulation as well as formal verification.
The register verification capabilities of IDS-Verify can be extended to pre-silicon and post-silicon validation. Agnisys IDS-Validate automatically generates both UVM and C/C++ sequences that exhaustively test your memories and registers. IDS-Validate also generates verification environments and user-defined functional tests to verify the functional behavior of custom design blocks.
The generated tests run in UVM-C hybrid environments, either on your SoC’s embedded processors or on RISC-V SweRV Core EH1 packaged with IDS-Validate. The generated C/C++ code also runs on physical boards, so IDS-Validate covers both initial pre-silicon validation and final post-silicon validation in the bring-up lab. Embedded programmers can use the C/C++ sequences to develop and test the SoC production software as well as device drivers.
Agnisys IDS-Integrate automates the assembly of your design blocks into a full SoC or FPGA. Hooking up thousands of blocks is a tedious and error-prone process if done manually. IDS-Integrate provides a flexible and customizable environment to meet the design requirements for a complete chip. It not only interconnects blocks, but it also automatically generates RTL components such as bus multiplexers, aggregators, and bridges.
Your are not limited to designs generated by IDesignSpec GDI and IDS-IPGen. IDS-Integrate can handle any third-party IP block with an IP-XACT description and can even handle your custom design blocks. You can specify in Tcl or Python how your blocks should be interconnected, including rules for intelligent name-mapping. To help you check your specifications, IDS-Integrate offers an intuitive graphical view of blocks and their connectivity with simple navigation through the chip hierarchy.
Agnisys IDS-IPGen automatically generates both standard and custom IP blocks for inclusion in an SoC or FPGA. IDS-IPGen includes a flexible library of IP generators for many commonly used design blocks. Customizable generation is highly preferable to fixed IP blocks, which may not meet your requirements without risky manual modifications. Currently available generators support standards such as AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPU, Timer, and UART.
IDS-IPGen also supports the specification of custom IP blocks in your application logic. You can specify finite state machines (FSMs), data paths, signals, and other relevant parts of the design. The generated custom and standard IP blocks can be interconnected using IDS-Integrate.