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The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys

Podcast

The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys

Dan is joined by Anupam Bakshi, founder and CEO of Agnisys. Anupam has more than two decades of experience implementing a wide range of products and services in the high tech industry.
An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development

Webinar

An Introduction to Correct-by-Construction Golden Specification-based IP/SoC Development

Learn about front-end automation advances that leverage an innovative register information management system for the capture and centralization of hardware functionality.
D&R Interview at DAC 23

Interview

D&R Interview at DAC 23

D&R Interview at DAC  23 with Anupam Bakshi - Founder & CEO at Agnisys, Inc.
IP-XACT 2022 - What's New?

Webinar

IP-XACT 2022 - What's New?

This webinar will highlight some of the capabilities of IP-XACT 2022 in Agnisys tools. We will offer a brief introduction to the IP-XACT standard for users who are new to it. Therefore, participating in this webinar will be beneficial for both new users and seasoned users of IP-XACT.
Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

Webinar

Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

This webinar will examine the techniques used to avoid metastability as signals cross from one clock domain to another
The Benefits Discretix Gained With IDesignSpec™

Case Study

The Benefits Discretix Gained With IDesignSpec™

IDesignSpec™ changes the way Discretix develops embedded security solutions and IP solutions. 
Specification Automation for IP/SoC Design, Verification, Firmware and Documentation

Presentation

Specification Automation for IP/SoC Design, Verification, Firmware and Documentation

Specification Automation for IP/SoC Design, Verification, Firmware and Documentation at DVCon US 2022
How Xingtera Created a Fast and Efficient Design Process With IDesignSpec

Case Study

How Xingtera Created a Fast and Efficient Design Process With IDesignSpec

Learn how IDesignSpec helped the company improve their semiconductor design productivity significantly.
Automating IP and SOC Verification

Presentation

Automating IP and SOC Verification

Learn about the challenges and opportunities for verification of IP and SoCs
Customer interview with Allegro Microsystems

Case Study

Customer interview with Allegro Microsystems

In this video customer interview, learn how Allegro Microsystems uses and benefits from Agnisys products.
Customer Interview with Analog Inference

Case Study

Customer Interview with Analog Inference

In this video customer interview, learn how Analog Inference uses and benefits from Agnisys products.
Customer Interview with Yellowbrick

Case Study

Customer Interview with Yellowbrick

In this video customer interview, learn how Yellowbrick benefits from Agnisys products.
Designing IP and Device Driver for RISC-V

Presentation

Designing IP and Device Driver for RISC-V

Developing and integrating IPs and device drivers with processor cores based on RISC-V is a daunting task that requires a lot of automation and expertise.
Auto-generate Implementation-level Sequences for Portable Stimulus Tools

Presentation

Auto-generate Implementation-level Sequences for Portable Stimulus Tools

Presentation about auto-generate implementation-level sequences for portable stimulus tools.
Using Machine Learning in Register Automation and Verification

Whitepaper

Using Machine Learning in Register Automation and Verification

In this paper, understand how machine learning can be applied to register automation and verification.
In pursuit of Faster Register Abstract Layer (RAL) Model

Whitepaper

In pursuit of Faster Register Abstract Layer (RAL) Model

This paper introduces the new approaches for register layer. These models are developed in order to overcome the performance issues of the traditional UVM RAL model.
Agnisys joins Amelia Dalton’s Virtual Verification Smorgasbord Fish Fry

Podcast

Agnisys joins Amelia Dalton’s Virtual Verification Smorgasbord Fish Fry

In this week’s Fish Fry, we’re gobbling down as much verification as we possibly can fit on our podcastin’ plate.
Interview with EDA Cafe at DAC 2018!

Interview

Interview with EDA Cafe at DAC 2018!

Sanjay Gangal interviews Anupam Bakshi, Agnisys Founder & CEO
IDesignSpec : Register Generator

Video

IDesignSpec : Register Generator

IDesignSpec is a Register Generator tool that enables you to quickly generate high-quality code right from your document editor.
Verifying Registers using UVM and IDesignSpec

Video

Verifying Registers using UVM and IDesignSpec

This video shows how IDesignSpec can be used to generate register models, customize the generated models and how to simulate and verify the registers in the design.
Specification to Realization from Agnisys to Xilinx Zedboard

Video

Specification to Realization from Agnisys to Xilinx Zedboard

Target Xilinx Zedboard and the Zync FPGA using Agnisys tools: IDesignSpec and ISequenceSpec for fastest Specification to Realization.
DVinsight – Design Verification Editor Checker for SV/UVM

Video

DVinsight – Design Verification Editor Checker for SV/UVM

DVinsight is a smart editor for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code.
Agnisys Product Overview

Video

Agnisys Product Overview

An overview of innovative software that solves complex design and verification problems for system development.
D&R Interview at DAC 22

Interview

D&R Interview at DAC 22

D&R Interview at DAC 22 with Anupam Bakshi - Founder & CEO at Agnisys, Inc.
Introduction to System RDL Part 1

Webinar

Introduction to System RDL Part 1

SystemRDL 2.0 Register Description Language is the industry standard from Accellera used for describing control/status registers and memories in circuit designs.
Introduction to System RDL Part 2

Webinar

Introduction to System RDL Part 2

SystemRDL 2.0 Register Description Language is the industry standard from Accellera used for describing control/status registers and memories in circuit designs.
IDesignSpec GDI for Safety-Critical Designs

Webinar

IDesignSpec GDI for Safety-Critical Designs

In this webinar we discussed how the IDesignSpec GDI FS tool helps teams to develop Functionally Safe designs.
Key Gochas in implementing CDC for various Bus Protocols

Whitepaper

Key Gochas in implementing CDC for various Bus Protocols

The paper will talk about the simulation results obtained for the implementation of a low power RTL design and techniques used for interconnection with various bus protocols.
AI Based Sequence Detection

Whitepaper

AI Based Sequence Detection

The article talks about the current state of development and gives ideas about how the reader can implement their own solution to achieve true specification driven software development.
CERN Selects Agnisys IDesignSpec for The TOTEM Experiment Project at the Large Hadron Collider

Case Study

CERN Selects Agnisys IDesignSpec for The TOTEM Experiment Project at the Large Hadron Collider

Learn how CERN uses Agnisys IDesignSpec for The TOTEM Experiment Project
Allegro Selects Agnisys IDesignSpec™ and ARV-Sim™ for Specification Creation, Automatic HDL and UVM Model Generation for Register and Memory Blocks

Case Study

Allegro Selects Agnisys IDesignSpec™ and ARV-Sim™ for Specification Creation, Automatic HDL and UVM Model Generation for Register and Memory Blocks

Learn how Allegro uses Agnisys IDesignSpec™ for Specification Creation, Automatic and UVM Model Generation.
IDS-NG for Formal Verification

Webinar

IDS-NG for Formal Verification

In this webinar we discuss the importance of auto-generating System Verilog Assertions
IDS- NG for system verification

Webinar

IDS- NG for system verification

This webinar discusses verification and validation of SoCs in general and specifically with IDS-NG.
IDS- NG for documentation

Webinar

IDS- NG for documentation

Chip/IP documentation is a critically important resource to save project time and effort.
IDS-NG for Firmware

Webinar

IDS-NG for Firmware

A sequence is an ordered set of transactions on various interfaces/ports of a device.
Centralized Register Design and Verification from a Golden Specification

Webinar

Centralized Register Design and Verification from a Golden Specification

How to bring the ease of a document editor to your system architects and designers to create an executable specification using IDesignSpec.
IP Connectivity and Smart Assembly Methodology for SoCs

Webinar

IP Connectivity and Smart Assembly Methodology for SoCs

How to automatically assemble and connect IPs from many different sources at your SoC level using SoC Enterprise.
From Cross-Platform Specification to Code Generation at the Enterprise Level

Webinar

From Cross-Platform Specification to Code Generation at the Enterprise Level

Capture your register and sequence specifications for IPs and SoCs from the individual IP to the enterprise level using IDS-NextGen.
A Complete UVM Automated Based Verification System

Webinar

A Complete UVM Automated Based Verification System

Automatically generate a complete UVM testbench for your addressable registers and application logic, including sequence items, configurations, checkers, coverage, and even the UVM plumbing, using Specta-AV™.
Automatic Creation of Pre Validated RTL for Highly Configurable IPs

Webinar

Automatic Creation of Pre Validated RTL for Highly Configurable IPs

How to automatically generate IPs designed to be easily customizable and configurable to meet your SoC requirements using the SLIP-G.
System-Level Validation with RISC-V Processors

Webinar

System-Level Validation with RISC-V Processors

How to stimulate your RTL design with synchronized SoC testbench and RISC-V embedded tests using Automatic SoC Verification and Validation (ASVV™).
An Easy Solution for Automated Register Verification

Webinar

An Easy Solution for Automated Register Verification

How to stress-test your registers in simulation by automatically generating your entire UVM testbench and supporting Make files for complete register verification using ARV-Sim.
Formal Verification of Registers and SoC Assembly in Collaboration with Jasper™ and OneSpin™

Webinar

Formal Verification of Registers and SoC Assembly in Collaboration with Jasper™ and OneSpin™

How to formally verify your design by automatically generating SystemVerilog Assertions (SVA) for your block-level register specifications, chip-level RTL, and RTL connectivity at the SoC level using ARV-Formal™
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