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IDesignSpecTM GDI
Next Generation Semiconductor Specification Automation

Agnisys IDesignSpec GDI (Graphical Design Interface) provides a complete solution for executable hierarchical specification of your memories, register sets, registers, and register fields in an IP or SoC. You can choose from a variety of input formats. You can import existing descriptions in standard formats such as SystemRDL, IP-XACT, JSON, RALF, YAML, XML, and comma-separated values (CSV) files.

Powerful Register, Memory Editor, SystemVerilog, UVM

You can specify the registers and memories using Agnisys-supplied templates and Add-ins for Microsoft Word, Microsoft Excel, or OpenOffice Calc.

For maximum benefit and flexibility, you can choose the highly intuitive specialized register and memory editor contained within IDesignSpec GDI, a graphical user interface (GUI) for specification entry. IDesignSpec GDI interactively generates a wide variety of output files for the teams on your project, supporting design, verification, embedded programming, validation, and documentation.

IDesignSpec GDI fits seamlessly into your SoC or IP development flow, including integration with the Git revision control system to manage both text and graphics files while fostering collaboration.

IDesignSpec GDI Data Flow 4

How IDesignSpec GDI Enhances Your Development Process

This executable specifications read by IDesignSpec GDI support simple registers as well as more than 400 special register types, including indirect, indexed, read-only/write-only, alias, lock, shadow, FIFO, buffer, interrupt, counter, paged, virtual, external, read/write pairs, and combinations of these types.


RTL generation of registers, memories, CDC logic, and advanced bus connectivity

From your specifications, IDesignSpec GDI interactively generates output files for your design, verification, software, and documentation teams. It generates the complete RTL description for the registers and memories, including a bus slave and decode logic specific to the user-selected bus protocol and any clock-domain-crossing (CDC) synchronization logic needed. This enables instant connection of the your design to the register bus. Supported interfaces include APB, AHB, AHB-Lite, AXI4, AXI4-Lite, TileLink, Avalon, Wishbone, and proprietary buses.

The generated SystemVerilog, Verilog, VHDL, or SystemC RTL code for the registers is human-readable with easy-to-follow comments. Your hardware design team simply adds the generated files to their list of hand-written application logic RTL blocks and third-party IP blocks for use with simulation, logic synthesis, and other tools in the development flow.


Generation of SystemVerilog testbench models and C/C++ headers

IDesignSpec GDI generates a SystemVerilog model compatible with the UVM standard and suitable for inclusion in your UVM testbench. This eliminates a lot of work on the part of your design and verification teams. IDesignSpec GDI helps your embedded programmers as well, by generating C/C++ headers for the memories, registers, and fields. This replaces tedious manual transcription of specification details into code and avoids any chance of errors in the process.


Generation of high-quality documentation from the specification

For your technical writers, IDesignSpec GDI generates high-quality documentation of registers and memories suitable for inclusion in user manuals. User-selectable formats include Microsoft Word, HTML, PDF, Markdown, and DITA.


Download the IDesignSpec Suite Brochure

View a summary of each product and how the suite enables your semiconductor teams to more rapidly develop products while improving efficiency.

Benefits of IDesignSpec GDI

The automatic generation of all these files for the project teams saves time and resources early in the project. Every file generated by IDesignSpec GDI is one that you do not have to code by hand. The correct-by-construction nature of specification generation also eliminates entire categories of bugs, accelerating verification and pre-silicon validation.

IDesignSpec GDI provides even more value every time that a specification changes:

  • Simple and automatic re-generation of all relevant files
  • Eliminates manual update effort and ensures that all your teams are always in sync
  • A common front end and interactive generation engine for all Agnisys products

What Our Clients Say

Ricky Lau
Ricky Lau
The Six Semiconductor CTA and Co-Founder
Our register specification changes constantly during most of our IP project schedule, and we simply re-run IDS to propagate those changes and re-generate the output files....
Michele Quinto
Michele Quinto
With IDesignSpec the product was very easy to use and development follows naturally after requirements and documentation; consistency between firmware and software code is guaranteed.
Bahaa Osman
Bahaa Osman
FABU America’s Verification TeamLeader
Our experience with IDesignSpec has been extremely positive. We were looking for a tool that could describe our registers in a user-friendly input format. ....
Alon Scheptol, Design Engineer
Alon Scheptol, Design Engineer
IDesignSpec is fully loaded with capabilities and usage simplicity combined with great support
Charles Qi, VP of Engineering
Charles Qi, VP of Engineering
Our Engineering team is convinced that Agnisys’ IDesignSpec is a great tool to help them improve their productivity significantly
Khalid Chishti, Sr. Design Engineering Manager
Khalid Chishti, Sr. Design Engineering Manager
Allegro Microsystems
Things change over time and I think the biggest value added for Agnisys for us has been changing of a spec and then generating code directly within minutes.
Teja Panchagnula, Verification Engineer
Teja Panchagnula, Verification Engineer
Analog Inference
IDesignSpec really fit … and it was pretty straightforward: the documentation, the support that they had, and even the registers that it created.
Paritosh Kulkarni, Lead Silicon and FPGA Architect
Paritosh Kulkarni, Lead Silicon and FPGA Architect
With Agnisys you have a single automated flow … I would say it has saved us many days and months over the past four years in not having to debug any issue related to registers.