Resources | Agnisys

Comparison between IP-XACT and SystemRDL

There are two standards developed by Accellera for capturing artifacts of the IP/SoC - IP-XACT and SystemRDL. Both of these standards have their strengths and weaknesses and the

IP-XACT

A Standard way to build IPs and SoC using IDesignSpec and IP-XACT

The two biggest challenge of today’s complex design are IP-Integration and Verification, and we would like to

SystemRDL

Nest Generation SystemRDL

Using IDesignSpec™ for register implementation

In pursuit of Faster Register Abstract Layer (RAL) Model

RAL is used to model the registers and memories present in the design. UVM comes with register package which is used to model these registers and memories. With its numerous

Using Machine Learning in Register Automation and Verification

Machine Learning (ML) is a powerful concept where trainable engine and a dataset can be made to predict future outputs. This concept has been leveraged to help users create IP

ML-Based Verification and Regression Automation

Verification is a labour-intensive work. Machine Learning (ML) algorithms can be used to eliminate the manual work. This paper shows ML techniques used to reduce or eliminate manual verification work

Key Gochas in implementing CDC for various Bus Protocols

In the industry where the designs are getting complex with huge hierarchy, there is often a requirement of multiple clock domains. But while, multiple clock domains exist various complications occurs,

AI-Based Sequence Detection

In this era of automation, significant advantages can be gained by automatically generating verification and validation sequences from natural language text using artificial intelligence (AI) based sequence detection techniques, and