SoC Design


SoC Design

Developing a modern system-on-chip (SoC) device is challenging in many ways, but it starts with the design. Without a design, there’s nothing to verify, program, or validate. The design begins as a register-transfer-level (RTL) description, is transformed into gates and transistors by logic synthesis and layout tools, and is ultimately fabricated in silicon.

SoC Design

IT all Starts with IP

Even a team with hundreds or thousands of designers cannot design today’s huge and complex SoCs from scratch. Even if such an approach was possible, it would be way too expensive and could not meet tight time-to-market (TTM) requirements. A contemporary SoC might have 90% or more of its RTL blocks reused from previous projects or licensed from intellectual property (IP) providers.
Commercial IP allows RTL designers to focus their efforts on the parts of the SoC that offer product differentiation rather than reinventing the wheel for common design blocks. However, a “one size fits all” approach for IP is too limiting. Many standards have choices such as data width, optional features, and provision for custom extensions.
The upshot is that IP must be configurable and customizable. This provides all the desired benefits in terms of schedule and cost savings while not limiting the end functionality and potential markets for chips. Designers have to be able to scale design parameters, select applicable options, and add their own teaks to the IP without manual editing.

IDS-IPGen Provides Configurable and Customizable IP

Agnisys provides a solution that meets the needs of SoC designers using commercial IP. IDS-IPGen™, part of the Agnisys IDesignSpec™ Suite, generates a broad range of RTL IP blocks that are common to many chip designs. Using a generative approach makes it easy for SoC designers to configure and customize the IP to meet the needs of their customers’ end applications.
IDS-IPGen lets designers choose many attributes of the generated IP, including the variations defined by any relevant standards. These may include bus widths, number of ports, and optional functionality. Designers make these choices using an intuitive graphical interface. If SoC requirements change at any point in the project, the designers can simply re-generate the IP with the desired options. 
Many of the functions supported by IDS-IPGen are complaint with widely adopted industry standards. Choosing reusable solutions for standards frees designers from having to become experts in all the details. Currently available functions for IP generation include AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPI, Timer, and UART.
Figure 8 Example of User Customization in IDS-IPGen_page-0001 (1)

IDS-IPGen Supports Custom IP

It is possible to imagine successful SoC using just a novel combination of commercial IP blocks, but that never happens. All chips contain at least some unique IP designed from scratch, and this is often the source of the biggest differentiation against competitors. Given the time and recourse constraints on SoC projects, designers are looking for help on custom IP as well as standard IP.
Agnisys provides a solution to this need. Even within novel block designs, there are many common elements that occur across many chips. Designers can generate finite state machines (FSMs) with IDS-IPGen, as well as registers and memories with IDesignSpec GDI and IDS-Batch CLI. These design elements are generated in RTL, ready for simulation and logic synthesis.
SoCs are hardware-software systems, and Agnisys provides help for programmers as well. In parallel with the RTL design, the IDesignSpec Suite generates the sequences necessary to configure and program the registers in the IP blocks. These sequences are provided in Universal Verification Methodology (UVM) form for verification and C/C++ code for validation and software development.

Hooking up IP Blocks Is a Pain

SoCs contain hundreds or thousands of design blocks, most of them replicated many times. In the final stages of RTL design, all these blocks must be connected together at the full-chip level. Manual hookup is tedious, time consuming, and subject to errors. A chip with 400 block instances, each with an average of 100 ports, requires 40,000 connections to be made.
Signals may run from leaf-level blocks up to the top level and then back down to other leaf blocks, with dozens of connections and renames along the way. Similar signal names exacerbate the problem. Multiple instantiations of blocks generally connect to signal names that differ only in prefixes or suffixes. It’s impossible to keep all of this in mind when typing in connections by hand. 
Just as with the specifications for IP blocks and registers, top-level hookup specifications change many times over the course of projects as designs and requirements evolve. The ripple effects of changing just a few blocks can be significant when scaled over many instantiations in large SoCs. Manual RTL editing is no longer an acceptable approach.

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IDS-Integrate Automates SoC Hookup

Agnisys provides a solution for this challenge as well. IDS-Integrate™, also part of the IDesignSpec Suite, automates the process of integrating IP blocks together to assemble and generate complete top-level RTL designs. Designers use a simple but powerful specification format, including wildcards to deal with similarly named signals, to describe the desired interconnections.


For IP blocks with standard buses such as AHB and APB, IDS-Integrate automatically generates RTL aggregators, bridges, and multiplexors as required to satisfy the interconnection specification. For example, AHB interfaces on two IP blocks can be aggregated into a single bus. If the design includes IP using the AHB system bus and IP with APB peripheral interfaces, IDS-Integrate automatically generates an AHB-to-APB bridge between the two buses.


Agnisys Automates SoC Design

To meet ever tighter TTM requirements for ever larger and more complex SoCs, designers can no longer write and interconnect all their RTL blocks by hand. Agnisys provides specification automation solutions that generate correct-by-construction RTL designs plus files to help with verification, validation, and software. The benefits of this automation are replicated every time that specifications change. The result is faster chip development with fewer resources and increased confidence.

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