IDesignSpec™ (IDS): Create Executable Design Code From The Specification – UVM Register Generator
IDesignSpec is an award-winning software that helps IP/SoC design architects and engineers create simple yet powerful specifications in MS Word, Excel or Libre Office. It captures simple as well as special registers, signals, interrupts and sequences, then generates synthesizable RTL code and interfaces to ARM AMBA® buses like AXI, AHB, APB, AHB3Lite and other standard buses. IDS provides the C/C++ header files and firmware codes and enables software teams to develop the device driver at the early stage of the design cycle.
IDS NextGen is a multi-platform product which helps user to create SoC specification at an enterprise level. It handles individual IP to sub-system to SoC level and is compatible with Word ,Excel, IP-XACT, RALF, CSV, System RDL. IDS NextGen generates design and verification code for not just registers but sequences in one integrated environment. It reduces the verification time by generating the entire UVM SV and SystemC output sequences.
A complete Integrated Software for SOC/IP teams who aims to cut down the verification and validation time. ASVV automatically generates UVM and C sequences which exhaustively tests the Memories and register maps. ASVV also provide a way to generate custom tests for boards, UVM and UVM-C based environments through a common specification. It provides a complete solution to a firmware Engineers to write and debug the device drivers and application software.
Specta-AV is a comprehensive UVM testbench generator that automates verification using an industry-proven code generation technology. With the ability to parse hierarchical register specification from IP-XACT, SystemRDL, Word, or Excel, and the capability to retarget complex sequences into various modeling language such as C and SystemVerilog, Specta-AV facilitates a methodology where multiple SoC groups can align and work from a golden specification for autogenerating UVM tests/environments/agents.
ARV™ – Automatic Register Verification – Simulation – Formal Verification
ARV is a complete Register Verification solution using complementary methodologies, simulation and formal. ARV helps to auto-generate UVM testbench, bus agents, monitors, drivers, adaptors, predictors, sequencers, and sequences, giving users the means to complete the verification right the first time. This verification plan allows easy back-annotation from the test results, allowing users to track the progress of verification efforts. ARV-Formal automatically generates assertions directly from the specification automating setup and ensuring a rapid return on investment.
ISequenceSpec enables users to describe programming and test sequences of a device and automatically generate sequences ready to use from an early design and verification stage to post-silicon validation. Sequences are a “set of steps” that involve writing/reading specific bit fields of the registers in the IP/SoC. These sequences can be simple, or complex involving conditional expressions, an array of registers, loops and more. ISequenceSpec helps the user write a single sequence specification and generate the UVM sequences for verification, Verilog sequences for validation and various output formats for Automatic Test Equipment (ATE).
In any System-on-Chip (SoC) design there are certain standard IPs that are nearly ubiquitous and are used across many designs. A designer, generally, has two alternatives – either to spend time creating these IPs from scratch to meet their custom requirements or get them off-the-shelf.
SoC Enterprise provides a flexible and customizable environment for SoC design assembly to comprehensively meet specific design requirements. It’s not just an assembler as it can also generate RTL components like bus-aggregators, bridges (AHB-APB, AXI-APB, AXI4Full-AHBFull), muxes and other “plumbing” components by leveraging already existing and mature register solution along with the new “Standard Library of customizable & configurable IP Generators” (SLIP-G™).
With DVinsight, users develop high-quality design verification code rapidly, efficiently and creatively. DVinsight is a smart editor for creating correct-by-construction, high-quality design verification testbench code. Code created with DVinsight is UVM standardized and bug free to avoid time-consuming and costly debugging later in the semiconductor development process. Because DVinsight helps design verification engineers create correct-by-construction testbench code, it benefits expert developers as well as beginners because it prevents simple mistakes and helps beginners decrease their SystemVerilog and UVM learning curve. See the DVinsight Press Release.
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