IDesignSpec™ (IDS): Create Executable Design Code From The Specification – UVM Register Generator
IDesignSpecis award-winning software that helps IP/SoC design architects and engineers create simple yet powerful specifications in MS Word, Excel or Libre Office. It captures simple as well as special registers, signals, interrupts and sequences, then generates synthesizable RTL code and interfaces to ARM AMBA® buses like AXI, AHB, APB, AHB3Lite and other standard buses. IDS provides the C/C++ header files and firmware codes and enables software teams to develop the device driver at the early stage of the design cycle.
ARV™ – Automatic Register Verification – Simulation – Formal Verification
ARV is a complete Register Verification solution using complementary methodologies, simulation and formal. ARV helps to auto generate UVM testbench, bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences, giving users the means to complete the verification right the first time. This verification plan allows easy back-annotation from the test results, allowing users track the progress of verification efforts. ARV-Formal automatically generates assertions directly from the specification automating setup and ensuring a rapid return on investment.
ISequenceSpec enables users to describe programming and test sequences of a device and automatically generate sequences ready to use from an early design and verification stage to post-silicon validation. Sequences are a “set of steps” that involve writing/reading specific bit fields of the registers in the IP/SoC. These sequences can be simple, or complex involving conditional expressions, array of registers, loops and more. ISequenceSpec helps the user write a single sequence specification and generate the UVM sequences for verification, Verilog sequences for validation and various output formats for Automatic Test Equipment (ATE).
With DVinsight, users develop high-quality design verification code rapidly, efficiently and creatively. DVinsight is a smart editor for creating correct-by-construction, high-quality design verification testbench code. Code created with DVinsight is UVM standardized and bug free to avoid time-consuming and costly debugging later in the semiconductor development process. Because DVinsight helps design verification engineers create correct-by-construction testbench code, it benefits expert developers as well as beginners because it prevents simple mistakes and helps beginners decrease their SystemVerilog and UVM learning curve. See the DVinsight Press Release.
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