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IDS-IPGenTM
Specification Automation for Standard and Custom IP Blocks

A typical SoC contains hundreds or thousands of RTL blocks from a variety of sources. Many chip companies maintain in-house libraries for commonly used design structures and interfaces. In addition, nearly all SoC projects also license IP blocks from partner companies or commercial IP providers, especially for blocks that implement a standard function such as AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPI, Timer, or UART.

Automatically Keep Your IP Blocks Synchronized with the Specification

Leveraging IP and reusing parts of previous designs can save your SoC project team a huge amount of time and effort. The downside of using fixed IP blocks is that you may not be able to get exactly what they want. It may be possible to modify and customize IP, but this incurs the risk of breaking the standard functionality. Agnisys IDS-IPGen solves this problem by automatically generating IP blocks from specifications that are highly configurable and customizable.

IDS-IPGen supports a wide variety of standard IP blocks as well as the specification of finite state machines (FSMs), data paths, signals, and other parts of your custom IP blocks. For both standard and custom blocks, IDS-IPGen generates RTL models, UVM verification models, and tests that provide high functional and code coverage right out-of-the-box.

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How IDS-IPGen Enhances Your Development Process

 

IDS-IPGen offers you the ability to choose many attributes of the IP design, including the options defined by any relevant standards. These may include bus widths, number of ports, optional functionality. The generator ensures that standards requirements are not compromised in the process of customization.

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Flexible library of standard IP generators

By taking advantage of specification automation, IDS-IPGen generates many output files to benefit your project teams. It includes a powerful and flexible library of standard IP generators. Each library title generates a customized RTL design to meet your requirements.

 

Improves IP adoption

The RTL code reflects the customized aspects of the design, which you specify in the IDesignSpec GDI unified GUI. Some naysayers on using IP maintain that the verification and validation work for an unfamiliar design takes more time than just doing the design yourself. IDS-IPGen eliminates this objection because it handles all aspects of the IP block in every stage of development.

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Download the IDesignSpec Suite Brochure

View a summary of each product and how the suite enables your semiconductor teams to more rapidly develop products while improving efficiency.

Benefits of IDS-IPGen

IDS-IPGen includes generators for numerous standard design blocks, including AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPI, Timer, and UART. Your developers do not have to learn the many details of these complex protocols. For both standard and custom blocks, your designers do not have to manually develop the IP RTL code. Your verification engineers do not have to develop IP models or tests and do not have to struggle to meet coverage goals. This saves enormous time and resources on your project and moves verification and validation earlier in the schedule.

What Our Clients Say

Ricky Lau
Ricky Lau
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The Six Semiconductor CTA and Co-Founder
Our register specification changes constantly during most of our IP project schedule, and we simply re-run IDS to propagate those changes and re-generate the output files....
Michele Quinto
Michele Quinto
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CERN
With IDesignSpec the product was very easy to use and development follows naturally after requirements and documentation; consistency between firmware and software code is guaranteed.
Bahaa Osman
Bahaa Osman
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FABU America’s Verification TeamLeader
Our experience with IDesignSpec has been extremely positive. We were looking for a tool that could describe our registers in a user-friendly input format. ....
Alon Scheptol, Design Engineer
Alon Scheptol, Design Engineer
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Discretix
IDesignSpec is fully loaded with capabilities and usage simplicity combined with great support
Charles Qi, VP of Engineering
Charles Qi, VP of Engineering
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Xingtera
Our Engineering team is convinced that Agnisys’ IDesignSpec is a great tool to help them improve their productivity significantly
Khalid Chishti, Sr. Design Engineering Manager
Khalid Chishti, Sr. Design Engineering Manager
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Allegro Microsystems
Things change over time and I think the biggest value added for Agnisys for us has been changing of a spec and then generating code directly within minutes.
Teja Panchagnula, Verification Engineer
Teja Panchagnula, Verification Engineer
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Analog Inference
IDesignSpec really fit … and it was pretty straightforward: the documentation, the support that they had, and even the registers that it created.
Paritosh Kulkarni, Lead Silicon and FPGA Architect
Paritosh Kulkarni, Lead Silicon and FPGA Architect
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Yellowbrick
With Agnisys you have a single automated flow … I would say it has saved us many days and months over the past four years in not having to debug any issue related to registers.