Solutions for Each Semiconductor Development Role

Agnisys offers solutions appropriate for each of your semiconductor development roles. These solutions simplify deployment and use by your development teams and provide an integrated approach to design, verification, and validation.

How Agnisys Eliminates Redundancies in Semiconductor Design, Verification, and Validation

Overcoming the weaknesses of traditional natural language specifications requires writing the specifications in a precise format rather than natural language, and making this format executable so that tools can generate as many files as possible for the design, verification, programming, validation, and documentation teams. Such a solution is available today.

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Product / Semiconductor Role Mapping

Architects

Designers

Verification Engineers

Firmware Programmers

Prototype Engineers

Bringup Engineers

Technical Writers

CAD & Process Engineers

Architect the Hardware-Software Interface and the Address Map using intutive graphical tool.

Architect the Hardware-Software Interface and the Address Map.

Generate SystemC models for complete IP *

Design the register map for IPs and SoCs using intutive graphical tool and generate RTL.

Design the register map for IPs and SoCs and generate RTL.

Assemble IP blocks to create SoCs and generate RTL.

Create IP blocks from Finite State Machine and Data path specification. Use IP from Agnisys Standard library. Generate RTL.

Generate UVM/RAL model for all types of registers and blocks.

Generates complete UVM based verification environment with register focused cover-groups and out-of-the box ~100% coverage. Create register tests and assertions including protocol compliance.

Generate complete Validation environment and C/C++ tests.Create custom UVM tests that can run in validation environments.

Automatically generate tests for IP that ensure close to 100% code and functional coverage.Generate UVM model for IPs.

Generate C/C++ header and documentation.

Generate C/C++ building blocks.

Generate C/C++ header and documentation.

Generate C/C++ tests for SoC validation.

Generate C/C++ header and documentation.

Create custom C/C++ tests that can run in verification and validation env.

Generate Address Map and register documentation

Generate standard IP-XACT, data dumps in various formats.Generate custom outputs using templates or Tcl/Python API.

Generate standard IP-XACT for IP/SoC.

How These Solutions Benefit Each User

Architects: Your architects use IDesignSpec GDI to specify registers and memories.

Designers: Your RTL designers use IDesignSpec GDI and IDS-Batch CLI to specify and generate RTL code for registers and memories. They use IDS-IPGen to configure, customize, and generate RTL code for standard IP blocks and to specify and generate RTL code for your custom IP blocks. Designers also use IDS-Integrate to generate RTL code for top-level chip interconnection of your standard and custom IP blocks.

Verification Engineers: Your verification team uses IDS-Verify and IDS-IPGen to generate a UVM testbench and tests and then simulate using generated and custom sequences. IDS-Verify also generates assertions for use in formal verification. Your verification engineers can optionally use IDesignSpec GDI to create and modify sequence specifications graphically.

Firmware Programmers: Your software and firmware programmers use IDS-Validate to generate C/C++ sequences as the basis for their device drivers and embedded code.

Prototype Engineers: Your prototyping team uses IDS-Validate to generate C/C++ driver and embedded code to run in an FPGA prototyping platform to perform pre-silicon hardware-software validation. They can also run the UVM testbench and embedded code together in a synchronized fashion in simulation to perform hardware-software co-verification.

Bringup Engineers: Your team in the bringup lab uses IDS-Validate to generate the same C/C++ driver and embedded code used in pre-silicon prototyping to run on the actual chip and perform post-silicon full system validation.

Technical Writers: Your technical publications team uses the documentation generated by IDesignSpec GDI and IDS-Batch CLI directly from the specification. This ensures that documentation is always up to date with the hardware and software and always in sync across all your project teams.

CAD & Process Engineers: CAD and Development Process Engineers benefit from the versatility of the IDesignSpec Suite. The various formats imported and exported by the products in the suite make it indispensable for legacy data and ever evolving future requirements. In addition, custom outputs can be generated using templates or the Tcl or Python API.

Solution for Safety-Critical Applications

The Agnisys IDesignSpec Suite has achieved the stringent tool qualification criteria defined in the ISO 26262 functional safety standard for road vehicles. The certificate also includes the IEC 61508 industrial functional safety standard. The process of certification by TÜV SÜD included an audit of the Agnisys safety management, tool development, and supporting processes. Agnisys products can be used in safety-critical flows with no certification effort by your development team. Agnisys helps designers meet the requirements of these standards by automatically generating the safety logic to detect and report faults. Based on your specification, IDesignSpec GDI or IDS-Batch CLI can generate the following types of safety logic included within the RTL design: parity bit, cyclic redundancy check (CRC), error correction code (ECC), and triple modular redundancy (TMR).

REQUST A FUNCTIONAL SAFETY SOLUTION OVERVIEW

Products that Streamline Semiconductor Development

The Agnisys product suite offers your product teams a closely linked set of products, including a unified graphical design interface (GDI) frontend and a unified generation engine. These can be shared across all teams to maximize efficiency and support fully automated flows.

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There is no better way to appreciate the power of the IDesignSpec Suite of products than to see it in action. Schedule your live solution demonstration today.

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Solutions that Span the IC Development Process