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Automated Chip Assembly from Specification

Manually hooking up hundreds or thousands of blocks into a top-level SoC design is a tedious and error-prone process. Many similarly named signals must be connected, with typographical errors certain to occur. The step-and-repeat hookup of repeated instantiations of the same block is especially tedious. Detecting interconnection errors occurs rather late in the project, only when full-chip simulation is ready. Runs are slow and memory intensive at this level, and debug is challenging given the enormous size of the design.

Automatically Maintain Interconnect Integrity as Specification Changes

Agnisys has a solution to apply specification automation to SoC-level assembly and interconnection. IDS-Integrate provides a flexible and customizable environment to meet the design requirements for your complete chip.

IDS-Integrate Data Flow 4

How IDS-Integrate Enhances Your Development Process


IDS-Integrate not only interconnects blocks, but it also generates RTL components such as bus multiplexers, aggregators, bridges (AHB to APB, AXI to APB, and AXI4-Full to AHB-Full), and other “plumbing” components as needed. As expected, IDS-Integrate fully comprehends the register RTL designs generated by IDesignSpec GDI and the IP blocks generated by IDS-IPGen.

You are not limited to designs generated by Agnisys. IDS-Integrate can handle any third-party IP block with an IP-XACT description and can even handle your custom design blocks. You can specify in Tcl or Python how your blocks should be interconnected, including rules for intelligent name-mapping between block input and output ports with identical or similar names. IDS-Integrate assembles the complete top-level SoC based on your specification.


Actions that you can perform with IDS-Integrate include:

  • Connecting an IDS-generated block with the your design block and creating a wrapper around it
  • Reading an IP-XACT component and connecting with the existing blocks
  • Connecting an AHB bus with an APB slave by automatically instantiating a bridge
  • Connecting several AHB blocks to an AHB master by automatically instantiating an aggregator
  • Moving a block from inside a deep hierarchy several levels higher
  • Generating SystemVerilog Assertions (SVA) for connectivity checks using formal verification

Download the IDesignSpec Suite Brochure

View a summary of each product and how the suite enables your semiconductor teams to more rapidly develop products while improving efficiency.

Benefits of IDS-Integrate

IDS-Integrate provides an automated, repeatable process that saves time and creates “correct-by-construction” SoC designs. It improves productivity of your design team by:

  • Eliminating manual coding errors when interconnecting RTL blocks
  • Helping users check their specifications
  • Providing an intuitive graphical view of blocks and their connectivity with simple navigation through the chip hierarchy
  • Saving time and resources throughout your project
  • Re-generating the top-level design at the push of a button every time a specification changes

What Our Clients Say

Ricky Lau
Ricky Lau
The Six Semiconductor CTA and Co-Founder
Our register specification changes constantly during most of our IP project schedule, and we simply re-run IDS to propagate those changes and re-generate the output files....
Michele Quinto
Michele Quinto
With IDesignSpec the product was very easy to use and development follows naturally after requirements and documentation; consistency between firmware and software code is guaranteed.
Bahaa Osman
Bahaa Osman
FABU America’s Verification TeamLeader
Our experience with IDesignSpec has been extremely positive. We were looking for a tool that could describe our registers in a user-friendly input format. ....
Alon Scheptol, Design Engineer
Alon Scheptol, Design Engineer
IDesignSpec is fully loaded with capabilities and usage simplicity combined with great support
Charles Qi, VP of Engineering
Charles Qi, VP of Engineering
Our Engineering team is convinced that Agnisys’ IDesignSpec is a great tool to help them improve their productivity significantly
Khalid Chishti, Sr. Design Engineering Manager
Khalid Chishti, Sr. Design Engineering Manager
Allegro Microsystems
Things change over time and I think the biggest value added for Agnisys for us has been changing of a spec and then generating code directly within minutes.
Teja Panchagnula, Verification Engineer
Teja Panchagnula, Verification Engineer
Analog Inference
IDesignSpec really fit … and it was pretty straightforward: the documentation, the support that they had, and even the registers that it created.
Paritosh Kulkarni, Lead Silicon and FPGA Architect
Paritosh Kulkarni, Lead Silicon and FPGA Architect
With Agnisys you have a single automated flow … I would say it has saved us many days and months over the past four years in not having to debug any issue related to registers.