IDS-Verify Goes Beyond Other Solutions
Given that UVM RAL is a standard, it is supported by many tools and vendors. However, no other solution is as broad or as powerful as IDS-Verify. There are hundreds of special register types used in SoC and IP designs today, including indirect, indexed, read-only/write-only, alias, lock, shadow, FIFO, buffer, interrupt, counter, paged, virtual, external, read/write pairs, and combinations of these.
IDS-Verify supports all these special types of registers, generating the specific tests needed for 100% verification coverage of each type. It also supports memories, generating new classes by extending the “uvm_mem” base class, instantiating them in the verification environment, and generating tests. Other unique UVM RAL features of IDS-Verify include:
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Support for multiple types of coverage models
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Support for cross-coverage, for example on two register fields
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Specification of custom coverage and constraints
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Generation of UVM callbacks for aliased registers
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Auto-mirroring to update the UVM register model when an RTL register is updated
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Optional registration of register and memory classes with the UVM “factory”
Agnisys Covers All the Bases
UVM is the widely accepted way to verify SoC and IP designs. Verifying the registers and memories in the design is one of the key aspects of this process. IP-Verify provides an unparalleled solution for UVM RAL automation, generating all files from standard descriptions. Every time that registers change as the design evolves, the UVM environment is regenerated at the push of a button.
IDS-Verify is just one component of the Agnisys IDesignSpec™ specification automation suite. Users can also generate C/C++ tests for register configuration and verification, hardware/software co-simulation environments, register documentation, and even the actual RTL register designs. There is simply no better solution for adding, verifying, programming, and validating IP and SoC registers.