Semiconductor Design and Verification Articles

As the ASICs are getting larger and more complex, the netlist simulation is becoming a veritably time-consuming process, and it isn’t worth running weeks of netlist simulations corresponding to a veritably small change ...

Ask a bunch of engineers about the Universal Verification Methodology (UVM) and you’ll hear two distinct sets of responses, sometimes from the same people.

SoC design needs automatic generation of hardware, software, testbenches, tests, and documentation from executable specifications.

Agnisys has customers designing all sorts of intellectual property (IP) blocks, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and system-on-chip (SoC) devices across a wide ...

A Standard way to build IPs and SoC using IDesignSpec and IP-XACT

Late last year, I published a blog post that summarized what had transpired for Agnisys over the course of 2021. That was an occasion to think about how much our company and our products have expanded over time. A few ...

As an electronic design automation (EDA) company, Agnisys provides many benefits for chip design and verification engineers. Our specification automation solution generates both the register transfer level (RTL) design ...

Typically thousands of registers are required for today’s complex designs, which are used to control the operations of the SOC.

As we close in on the final days of 2021, I can’t help but think back over the events of the year and offer a few observations. At the front of my mind is the recent Design Automation Conference (DAC) in San Francisco. ...

Most engineers involved in the design, verification, and validation of electronic systems are familiar with the Design Automation Conference (DAC). It’s the stimulating combination of a highly technical conference with ...

Just about a year ago, I published a blog post about the emerging need for better functional safety and security in a wide range of electronic products. We recently held a webinar on functional safety and how we enable ...

As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate the SystemVerilog RTL design, Universal Verification Methodology (UVM) ...

I hope that you’ve been able to attend or watch the recordings of the sessions in our latest webinar series on specification automation. We’re focusing on the requirements for different project teams and different tasks ...

In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars on how specification automation benefits many teams developing intellectual property (IP) blocks and system-on-chip (SoC) ...

If there’s one good thing to emerge amid all the challenges of the last year and a half, it’s improved technology for remote learning. On-line talks, webinars, and podcasts are nothing new, but with so many people ...

In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has proven to be quite popular with our users, and that’s not surprising. Reuse plays a big role in ...

It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology (UVM). After decades of ad hoc designer-centric simulation and a few advanced ...

The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed in my last post, we held our first Agnisys User Group Educational Roundtable (AUGER) on March 18. We had a great ...

In my last post, I discussed the importance of partners to the EDA industry in general, and to Agnisys in particular. Partnerships exist because our users demand them. In today’s post I’d like to focus on a group even ...

Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular. When I thought about writing a blog post on this topic, I asked myself whether this might be of ...

Electronics in general, and embedded systems in particular, become more critical every day. There is hardly a single aspect of our lives that is not controlled, monitored, or connected by embedded systems. Even ...

Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC) automation, including three new products announced at this year’s virtual Design Automation ...

Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and verification. Today’s designers operate very differently than their ...

A couple of years ago at the Design Automation Conference (DAC), as I walked the exhibit floor I was amused by how many EDA vendors had jumped on the marketing bandwagon for artificial intelligence (AI) and machine ...

In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world of semiconductor ...

Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification, you can generate ...

In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators (SLIP-G™), and IDS NextGen™ (IDS-NG) ...

Recapping a virtual event where new solutions were unveiled.

Anyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference (DAC). This event dates back 57 years, a long time for anything to last in our high-tech world. ...

System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design, and verification are all challenging. This blog post focuses on the ...

Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides a ...

A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the key ...

Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But few of us have experience dealing with a challenge as broad and disruptive as the COVID-19 global ...

Modern RTL design verification (DV) environments are both very powerful and very complex. They include advanced simulation testbenches plus support for formal verification, virtual prototypes, and emulation technology. ...

The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course, the various technologies for the automotive industry has led to a new ...

By Louie De Luna, Agnisys Chief Product Evangelist The idea of an open-source CPU core was virtually unheard-of ten years ago – let alone using it for commercial applications. The CPU core has been the most critical ...

By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades, but with the advent of AI applications and big data the entire ...

By Louie De Luna, Agnisys Chief Product Evangelist Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t really appreciate the impact of the ...

1981 marked the beginning of EDA as an industry. Within a few years there were many companies specializing in EDA, each with a slightly different emphasis.

Using abstraction, designers are able to focus on the high-level design & tests while the tools took care of the automation at the low-level.

By Louie De Luna, Agnisys Director of Sales and Marketing Right after Google’s AlphaGo system defeated a human Go world champion in 2015, the hype of deep learning and machine learning (ML) was quickly assimilated into ...

By Louie De Luna, Agnisys Director of Sales and Marketing Tools are made to automate a process, perform calculations, minimize errors and improve efficiencies, but at their core, tools are made to solve a given problem. ...

Every year we take a look back at the resources we’ve created to determine what you’ve found most useful. We invite you to take a look below at our top viewed and downloaded resources from 2018. RECORDED ...

 By Louie de Luna, Agnisys Director of Sales and Marketing UVM has certainly improved reusability of verification environments for SoC projects, significantly lowering the verification costs throughout the electronics ...

By Louie de Luna, Agnisys Director of North American Sales and Marketing Functional flaws in our everyday electronics are annoying. Internet routers can suddenly stop working, or our smart phones can suddenly freeze. ...

As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a bit of tunnel vision as we busy ourselves with client meetings, conferences, socializing with potential new clients, ...

This was an intriguing DAC. Hardware-Software Interface (HSI) is increasingly emerging as an area of importance.

With the ability to read in the Dulog format, users can create code from a specification and experience faster RTL and more versatile UVM.

Why Machine Learning Matters Machine learning (or “ML” for short) may have begun life as something of a buzzword, but it has long since proven itself to be anything but. At its core, the term itself describes a ...

The Intersection of Functional Safety and Electronic Design In an industry that has gone through an incredibly rapid transformation over the past few years alone, auto manufacturers all over the world have had to ...

Verification and Validation are two sides of the same coin In 2011, Intel discovered a design flaw in its Sandy Bridge combination graphics-microprocessor chip that led to not only a major production delay but that ...

Participating in DVCon has always been a wonderful experience for us as an organization. We had a great response and superb interaction with some of the most amazing leaders from the semiconductor industry. We were ...

I’m yet to meet a person who doesn’t like simplicity in engineering. I do believe that   Electronic Design Automation (EDA) products should be designed in an elegant way,     with minimum over-reach. They should let the ...

Agnisys will showcase IDesignSpec NextGen – the Next Generation product for  capturing requirement specification for embedded designs, and automatically  generating code from it. IDS NextGen is a multi-platform product ...

Machine Learning (ML) is the rage these days and we were not untouched by it. Being immersed in Specifications and dealing with customer queries about register and   sequence specification on a daily basis, we thought, ...

Machine learning has begun to have a huge impact on the EDA Industry. Numerous organizations are heading forward with home grown machine learning algorithm in order to make specification better. Agnisys is making ...

Consolidation is a not a totally new phenomenon for semiconductor Industry. Although the industry has shown no consolidation through almost all its history

The UVM register model is an essential component of the UVM based verification for modern designs. In this article we discuss the various paths to create UVM register model. We at Agnisys help teams automatically ...

In engineering, we often go about our work not knowing how that work touches others’ life and society in general. However, when you come to know about the impact this work has created, it is quite gratifying and ...

We all have different tastes, different habits and when it comes to work we like to work in different environments using different operating systems.

After almost a decade of focusing on SV, UVM, SystemC to build software products and teaching advanced verification/modeling to hordes of professionals, Agnisys has launched its consulting division to address the dire ...

Hardware is verified using simulators. Software compiled and debugged using compilers and debuggers. When it comes to the hardware/software interface, it’s not so straightforward. The FPGA development process can be ...

The Design Automation Conference is over for the year. Attendee leads or inquiries, to be more precise, have been collected and booths stored away for next year. The EDA industry has left the Austin Convention Center.   ...

Whether dealing with SoCs or a disaster in space, determining the correct set of steps is vital. No project team wants a “Houston, we have a problem,” moment. And yet, they happen all too frequently, even though there ...

While more registers means more functionality and configurability, more is not always better. No one gives much thought to the heating, ventilation and air conditioning registers in the house–typically, two in each ...

Important observations from Einstein and New England’s ice traders.. Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several ...

The DVCon Conference this year, was quite eventful for us with a lots of visitors at our booth. We were excited about the interest shown for IDesignSpec™ and our new product ISequenceSpec™ (ISS) – “Portable Sequence ...

Wow what a marvelous year 2015 has been to Agnisys, with full of events at the various technical exhibitions, new customers, new features and new products and not to forget – new partnership. It would be unfair to say ...

The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but a few who were genuinely interested in Agnisys. Since it was our first foray into ARM TechCon, it was good to meet new set of ...

Somewhere in the deep trenches of a UVM based verification project, an engineer teeters on the verge of insanity. As the saying goes, the faint of heart need not attempt UVM based verification. But what makes it so ...

In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If we take a look at the AMBA®AXI4Lite bus protocol, it has different channels for ...

Moore’s law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of technology. But, along with this, a new complexity takes shape in the form of documentation for ...

Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher levels of productivity. I find that interesting as we at Agnisys have been doing this left shift since ...

With the Design Automation Conference wrapping up this week in San Francisco, there is one thing we can say for sure – Automatic Register Verification (ARV) gains acceptance with design and verification teams. Last ...

We talk about creation of complex registers in IDesignSpec, generation of their suitable RTL and UVM models. The Software addressable registers in your design do not always just have simple read-write access. Sometimes ...

Agnisys just released DVInsight-Pro version 2.0 with many new features that enable much more productive SV/UVM code development.  

So we have been working in the register specification space for a long time. We came out with the IDesignSpec tool around 2010. Five years of constant refinement and evolution based on the customer feedback has created ...

The Large Hadron Collider (LHC) at CERN is the world's largest and most powerful particle accelerator. They have adopted Agnisys producs.

I feel like a bumblebee, going from the DVCon in US, to the next one in India to then to Europe.  All this cross-pollination is exciting and enriching when experiencing the needs of the Semiconductor design engineers ...

DVCon had a solid start in Bangaluru, India.  The audited attendee numbers will be coming in later, but we believe we had approximately 425+ delegates. That is truly amazing for the first year of the event! For me, it ...

It is penultimate day – the day before the big event! Preparing and launching the first ever DVCon India event feels like taxiing a plane down the runway, ready to take off.  It is new; the design was replicated from ...

Register Generation is a Must-Have Capability Today’s SoC designs contain several thousands of registers and memory map elements. The design team must, from the architecture, create the register and memory map ...

Modern SoCs get more and more complicated each and every day.  As the complexity of modern electronic semiconductor device design increases, niche tools for every nook and cranny of the design process emerge to help ...

Ending the last day of DAC strong with a presentation of DVinsight, a Universal Verification Methodology IDE The highlight of the last day at DAC was my presentation at the verification academy booth.  I presented ...

System on Chip Design Challenges – The Highlight of DAC Day 2 It was a very busy day for Agnisys on the second day of the Design Automation Conference. On day two, we learned how much our products address System on Chip ...

The first day of the DAC for Agnisys was exciting.  We experienced a higher traffic than during previous years.

As an EDA company our development cycle seems to revolve around DVCon and DAC. This year DVCon and DAC came fairly close together. I feel, we just finished DVCon and now we are preparing for DAC. Come to think of it, ...

DVCon 2014 was a wrap. It was marked by record attendance and participation both by the DV Community and the exhibiting vendors. Enthused, the Accellera team is now forging new frontiers with the DVCon brand name into ...

Here we go! The Design and Verification Conference (DVCON 2014) is round the corner. Make sure you register for the event which has been one of the premier conferences for IC design and verification engineers. This ...

Recently at the sidelines of DAC, Anupam Bakshi, CEO of Agnisys, Inc. sat down with Karen Bartleson, Director of Community Marketing at Synopsys to discuss a very important topic that is close to the heart of the ...

IDesignSpec generates several outputs from a single spec, evolving into an executable spec tool for digital design. Here's how we ensure its quality.

Published on 05-19-2013 07:30 PM in Semiwiki It goes without saying that registers play a vital role in designing any ASIC, FPGA, SoC or System. In today’s world, while designing SoC with multiple IPs and ...

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs ...

Launching new capability to specify Sequences in IDesignSpec

The buck stops at the CEO. DVCon 2012 happenings from our perspective.

So the cat is out of the bag. We are working on an assertion tool. This DVCon we turned quite a few heads when we announced our new assertion product IAssertSpec. Not that the tool is ready by any stretch of the ...

It's heartening to see greater cooperation between various EDA companies, both big and small. The ongoing work under Accellera for UVM, UCIS and IP-XACT is testament to this fact.  It is often bemusing to see the push ...

This article lists out ways to improve regression run time for hardware design verification.

Going to DAC had a boosting effect on us.

Started blogging again, this time from our own blogging site. Its DAC time of the year again. This will be our 2nd year in a row at DAC. Hopefully we have learned from our mistakes and won’t be repeating them this year. ...

We had a great first day at DAC. All the talk about recession and economic doom were hard to believe. People were enthusiastic and upbeat. Even the guys and gals looking for work were upbeat and were considering it to ...

I’m thrilled. Finally, we have a customer who sees the value that IDesignSpec brings for his company. We are indeed thankful to them for trusting our technology. I think this is validation of the concepts on which this ...

Business schools teach us that the way to set the price on a product has nothing to do with the cost. You sell it at a price that the market can afford. Semiconductor industry was able to afford heavy price tags on EDA ...

As you know we have created a brand new EDA tool that saves people a lot of time and money. Ok you have heard that before. But this is real 🙂 Ok so you have heard *that* before too! So how do I convince you to take a ...

I’m so excited … After years of work, my team and I have converted a word processor into an Engineering tool. Its like the Gene in Arabian Nights who says ” your wish is my command” … except in this case, your word is ...