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Blog

Three Steps to Set Up a RISC-V SoC UVM Testbench

June 17, 2020 Uttam Sarkar

Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides

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Automation of the UVM Register Abstraction Layer

May 28, 2020 Uttam Sarkar

A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the

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Doing What We Can in Challenging Times

May 9, 2020 Uttam Sarkar

Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But few of us have experience dealing with a challenge as

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Correct-By-Construction SystemVerilog UVM Testbenches

April 23, 2020 Uttam Sarkar

Modern RTL design verification (DV) environments are both very powerful and very complex. They include advanced simulation testbenches plus support for formal verification, virtual prototypes, and emulation technology. Even within

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Adopting New Methods For Faster Development Of RISC-V based SoCs

December 9, 2019 marketing@agnisys.com

The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course, the various technologies for the automotive industry has led to

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Creating Test Sequences for RISC-V Cores and SoCs

October 7, 2019 marketing@agnisys.com

By Louie De Luna, Agnisys Chief Product Evangelist The idea of an open-source CPU core was virtually unheard-of ten years ago - let alone using it for commercial applications. The CPU

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Repurposing von Neumann Architecture with SRAM-based Register Files

August 11, 2019 marketing@agnisys.com

By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades, but with the advent of AI applications and big

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Not your Average UVM Testbench Generator – Unveiling at DAC 2019

May 20, 2019 marketing@agnisys.com

By Louie De Luna, Agnisys Chief Product Evangelist Being so immersed in the work and technology, it’s easy to forget where we are in this technological revolution. Some of us didn’t

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EDA Is Advancing – but Where Are the Women?

April 15, 2019 marketing@agnisys.com

By Ishanee Bajpai - Senior Marketing Executive, Agnisys 1981 marked the beginning of EDA as an industry. Within a few years there were many companies specializing in EDA, each with a

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Setting the Stage for the Next Abstraction

March 26, 2019 marketing@agnisys.com

By Louie De Luna, Agnisys Chief Product Evangelist As generations of designs evolved from a few hundred transistors to hundreds of billions, our industry abstracted the problem space from transistors to

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Recent Posts
  • A Unified Development Flow for Embedded Systems
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  • A Unified Flow for Embedded Systems Development
  • Automatic Handling of Register Clock Domain Crossings
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