Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and verification. Today’s designers operate very differently than their predecessors who
Read moreIn February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM). It’s no exaggeration to say that UVM changed the world
Read moreRegular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and documentation of registers in chip designs. From a single specification,
Read moreIn my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this year: SoC Enterprise™ (SoC-E), Standard Library of IP Generators
Read moreIn my last blog post, I talked a bit about the history of the annual Design Automation Conference (DAC) and mentioned that this year it would be a virtual
Read moreAnyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference (DAC). This event dates back 57 years, a long time
Read moreSystem-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design, and verification are all challenging. This blog post focuses on the challenges faced
Read moreVerifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides
Read moreA recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the
Read moreMost of us have faced difficulties in our personal and professional lives, and have worked our way through them. But few of us have experience dealing with a challenge as
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