A Quick Look Back at a Virtual DAC
In my last blog post, I talked a bit about the history of the annual Design Automation Conference (DAC) and mentioned that this year it would be a virtual
Read moreDAC May Be Virtual, but Our New Products Are Not
Anyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference (DAC). This event dates back 57 years, a long time
Read moreSmart Assembly of SoC Designs
System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design, and verification are all challenging. This blog post focuses on the challenges faced
Read moreThree Steps to Set Up a RISC-V SoC UVM Testbench
Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one or more embedded processors, and the code they execute provides
Read moreAutomation of the UVM Register Abstraction Layer
A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based Universal Verification Methodology (UVM) standard provides most of the
Read moreDoing What We Can in Challenging Times
Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But few of us have experience dealing with a challenge as
Read moreCorrect-By-Construction SystemVerilog UVM Testbenches
Modern RTL design verification (DV) environments are both very powerful and very complex. They include advanced simulation testbenches plus support for formal verification, virtual prototypes, and emulation technology. Even within
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Adopting New Methods For Faster Development Of RISC-V based SoCs
The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course, the various technologies for the automotive industry has led to
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Creating Test Sequences for RISC-V Cores and SoCs
By Louie De Luna, Agnisys Chief Product Evangelist The idea of an open-source CPU core was virtually unheard-of ten years ago - let alone using it for commercial applications. The CPU
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Repurposing von Neumann Architecture with SRAM-based Register Files
By Louie De Luna, Agnisys Chief Product Evangelist The conventional von Neumann architecture has been the workhorse of computing for several decades, but with the advent of AI applications and big
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