SEMICONDUCTOR DESIGN AND VERIFICATION ARTICLES

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Too Many Iterations? How to Avoid Three Common Problems in Semiconductor Design

Developing semiconductor intellectual property (IP), system-on-chip (SoC) designs, and complete systems is enormously challenging. Even a small error in the...

Taking the First Step in Portable Stimulus Adoption

As chips get ever larger and more complex, one thing is for certain: the electronic design automation (EDA) tools, techniques...

Six Smart Ways Specification Automation Reduces Register Implementation Time

Modern system-on-chip (SoC) devices get more and more complicated each and every day. As the size and complexity of modern electronic...

Expanding the Scope of Specification Automation

Late last year, I published a blog post that summarized what had transpired for Agnisys over the course of 2021...

How safe is your ride?

The Intersection of Functional Safety and Electronic Design In an industry that has gone through an incredibly rapid transformation over...

Automatic Handling of Register Clock Domain Crossings

Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and...

Agnisys Commitment to Customer Success: A Competitive Advantage

The Agnisys IDesignSpec™ Suite offers development teams a closely linked set of products, including a unified graphical design interface (GDI)...

Different flows for UVM Register Generation

The UVM register model is an essential component of the UVM-based verification for modern designs. In this article, we discuss...

Power of SystemRDL to IP-XACT Conversion: Streamlining IP Integration

In the ever-evolving landscape of semiconductor and electronic design, the pursuit of efficiency, consistency, and reusability remains paramount. Designers frequently...
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