Silicon IP Portfolio
Silicon IP Portfolio
Ready-to-integrate bus, bridge, conversion, and interconnect IP for SoC and ASIC design.
The Agnisys Silicon IP Portfolio is a comprehensive set of silicon-proven interface IP that integrates directly into your SoC and ASIC development projects.
Bus targets, bridges, decoders, converters, crossbars, and Network-on-Chip — every block is FPGA-validated, third-party verified, configurable through IDesignSpec, and delivered in encrypted or plain-text form.
Silicon-Proven · 3rd-Party Verified · FPGA Validated · Configured via IDesignSpec
Bus infrastructure is the hidden cost of every SoC. Interconnect, bridges, and decoders are re-implemented and re-verified by hand on project after project — repetitive work that is easy to break and a direct risk to your tape-out schedule. Interconnect issues tend to surface late, close to silicon, where they are most expensive to fix.
The Agnisys Silicon IP Portfolio removes that risk. Every block arrives pre-verified and ready to drop in, so your team spends its time on differentiated logic instead of rebuilding standard bus plumbing.
One Portfolio, Every On-Chip Protocol
The portfolio is organised into three connected groups that cover the full interconnect stack:
- Bus Target IP — silicon-proven target interfaces for every major on-chip protocol.
- Bridges, Decoders & Converters — connect heterogeneous protocols and bus widths without touching your core RTL.
- Interconnect Fabrics — scale from a handful of masters to chiplet-class SoCs.
All IP is third-party verified and silicon/FPGA validated, and available in both encrypted and plain-text forms.
Bus Target IP
Silicon-proven target interfaces for every major on-chip protocol.
AMBA APB3 / APB4
A low-cost, non-pipelined bus for accessing the programmable control registers of peripheral devices.
Features: wait states · error reporting · transaction protection · sparse data transfer · flopped and non-flopped · synchronous or asynchronous reset
Applications: UART, GPIO, timers, I2C/SPI, CSR access
AMBA AHB3-Lite / Full
A high-performance, synthesizable bus for memory and high-bandwidth peripherals.
Features: burst transfers · single clock-edge operation · non-tristate implementation · flopped and non-flopped outputs · low data latency
Applications: SRAM/ROM controllers, DMA subsystems, memory bridges
AMBA AXI4-Lite / Full · AXI5-Lite
A high-bandwidth parallel bus with independent read and write channels for the most demanding subsystems.
Features: multiple outstanding addresses on a single ID · unaligned data transfers · out-of-order transaction completion · configurable wait states
Applications: CPU/GPU subsystems, AI accelerators, high-bandwidth memory controllers
Wishbone
A portable, open interconnection architecture for reusable IP cores, promoting design reuse and vendor neutrality.
Features: flopped and non-flopped · synchronous or asynchronous reset · single-clock data transfers · configurable latency
Applications: open-source and RISC-V SoCs, vendor-neutral IP reuse
Avalon
The native interface for connecting components in Intel FPGAs, supporting register, memory, and streaming access.
Features: synchronous or asynchronous reset · burst and non-burst transfers · byte enabling · configurable latency
Applications: Intel/Altera FPGA designs, Platform Designer (Qsys) systems
TileLink TL-UL 1.7 / 1.8
A chip-scale, multi-master, memory-mapped fabric that provides low-latency, high-throughput transfers.
Features: PutFullData · PutPartialData · Get · AccessAck · AccessAckData · error responses · with and without latency transactions
Applications: RISC-V multicore SoCs, Rocket Chip / Chipyard designs
Bridges, Decoders & Converters
Connect any protocol to any other, and any bus width to any other, without touching your core RTL.
Bus Decoders
Decoder logic routes each initiator transaction to the correct target and produces error responses for unmapped addresses in the hierarchy.
Supported buses: APB · AHB · AXI · TileLink
Features: flopped and non-flopped · seamless third-party IP integration
Bus Bridges
Lossless protocol bridging across AMBA generations, so mixed-protocol IP can communicate safely and without loss of data.
Six bridge pairs: AXI4 / AXI4-Lite → APB · AHB3(-Lite) → APB · AXI4 ↔ AXI4-Lite · AXI4-Lite → AHB3-Lite · AXI4 → AHB3 · TileLink 1.8 → APB
Common features: independent read and write channels · burst transfers · single clock-edge operation · non-tristate implementation · synchronous or asynchronous reset · configurable wait states
Bus Converters
The bus converter transforms wide initiator data buses to narrower target data buses, or the reverse, using external logic only — with no internal design changes.
Width conversion (both directions): APB 16 / 32-bit · AHB 32 / 64-bit · AXI 64 / 256-bit
Applications: mixed bus-width subsystems, legacy peripheral reuse
Interconnect Fabrics
Scale from a few masters to full chiplet-class SoCs.
Crossbar Interconnect
A multi-initiator, multi-target fabric with configurable arbitration, connecting many masters to many targets in a single system.
Features: up to 16 initiator interfaces and 8 target interfaces · priority, round-robin, and fixed arbitration · 32-bit data width for APB and AHB · 64-bit data width for AXI
Applications: multi-core backbones, shared-memory subsystems
Supported buses: APB · AHB · AXI
Network-on-Chip (NoC)
A scalable, packet-routed communication fabric that distributes routing and arbitration across the network, enabling higher bandwidth, better scalability, and improved power efficiency for large SoCs.
Supported buses: AHB · AXI4 · AXI5
Features: packetizer / depacketizer · routing engine · switch fabric · flow-control logic · QoS / arbitration · best integration with Agnisys register and integration tools
Applications: many-core SoCs, chiplets, AI and data-center fabrics
Configured Through IDesignSpec
Agnisys IP is not static. Every block is configured and, where needed, regenerated through IDesignSpec — the specification-driven tool at the heart of the Agnisys platform.
That means each IP is tailored to your design: reset type (synchronous or asynchronous), register flopping, bus variant, data width, wait states, and fabric arbitration are all configurable. When your specification changes, the IP is regenerated to match, keeping design and verification in sync.
Change the spec. Regenerate the IP. Everything stays consistent.
Where It Fits
The portfolio provides the interconnect, bridging, and fabric IP that sits between your cores, memories, and peripherals — the standard bus infrastructure of a modern SoC. Your team focuses on cores and application logic while Agnisys IP handles the plumbing: bus target interfaces, protocol bridges and decoders, width converters, and the crossbar or NoC that ties it all together.
Why Agnisys IP
- Faster integration — ready-to-integrate, pre-verified blocks drop straight into your SoC.
- Fewer errors — silicon-proven and third-party verified, so bugs don’t reach tape-out.
- Faster to silicon — configure and regenerate instead of hand-coding and re-verifying RTL.
- Full protocol coverage — AMBA, Wishbone, Avalon, and TileLink, plus bridges, converters, and interconnect fabrics.
- Flexible delivery — available encrypted or plain-text, for any development environment.
Delivery
All IP in the portfolio is third-party verified and silicon/FPGA validated, and can be delivered in encrypted or plain-text form to suit your workflow and security requirements.
Ready to Accelerate Your SoC Integration?
Talk to us about the bus, bridge, conversion, and interconnect IP your next SoC needs, and how it plugs into the Agnisys platform.
