AI Accelerators
High-bandwidth, low-latency interconnect for neural processing units and ML inference engines
NoC Interconnect IP Generator
IDS-NoC™
Multi-Protocol AMBA SupportAdvanced Routing & ArbitrationVirtual Channel Deadlock AvoidanceUnlimited Scaling
IDS-NoC™ is a scalable Network-on-Chip (NoC) interconnect IP generation solution for modern heterogeneous multi-core SoCs. Built on a packet-switched, distributed architecture, IDS-NoC enables engineering teams to rapidly create, configure, and integrate high-performance interconnect fabrics while eliminating the scalability, timing, and integration limitations of traditional crossbar-based designs. The solution is compatible with Arm® and RISC-V® processor-based systems and supports the development of complex, data-intensive SoCs.
Whether designing an AI accelerator, automotive SoC, multi-core platform, or edge computing device, IDS-NoC provides the scalability, predictability, and automation you need to ship complex SoCs faster.
Packet-switched fabric / live route
From Crossbar Bottlenecks to Scalable NoC
Traditional crossbar interconnects reach their limits as SoC complexity, core counts, and bandwidth requirements grow. IDS-NoC is architected to solve the hardest interconnect challenges teams face today:
Centralized switch matrixDistributed router links
Industry ChallengeAgnisys IDS-NoC Solution
Wiring CongestionPacket-switched distributed routing eliminates centralized wiring bottlenecks
Timing ClosureDistributed router paths shorten combinational paths and simplify closure
Scalability LimitsMesh topology scales linearly; add routers without redesigning the fabric
DeadlocksDedicated Virtual Channels per AXI transaction type prevent deadlock
High Power/AreaModular architecture minimizes die area and reduces power overhead
Heterogeneous IntegrationConnects processors, accelerators, memories, and peripherals through a scalable packet-switched fabric
Scalable N x M NoC Block Diagram for AMBA (AXI) Bus
Key Features
IDS-NoC delivers a complete, production-ready NoC fabric with the following capabilities:
FeatureDetails
Multi-Protocol Bus SupportAMBA- AXI4, AHB4, APB, AXI5, ACE
Mesh TopologyN×M mesh with N/S/E/W/Local port routing; linear area scaling, simplified timing closure
Virtual Channel Architecture4 independent VCs (AW/W, B, AR, R); structural deadlock elimination; full QoS configurability
Network Interface (NI)packetizer AXI <-> FLIT, depacketizer FLIT <-> AXI; Ingress & Egress NI per endpoint
Pipelined Router ArchitectureInput Buffers (FIFO), Routing Computation (RC), Virtual Channel Allocator (VCA), Switch Allocator (SA), Crossbar, Output Buffers (FIFO)
Wide Data BusUp to 2048-bit data bus width
Transaction DepthUp to 1024 pending transactions supported
ParameterizationGeneration-time, elaboration-time, and run-time configurability
Memory Re-order BufferOptimizes memory transaction ordering to improve bandwidth utilization and overall system performance.
OptimizationsPower management, security, address & data protection, advanced in-circuit debug
Functional Safety & ReliabilityReliability option, Functional Safety
Unlimited ScalingUnlimited NoC instances per design; unlimited Network Interface Units (NIs) per die
RTL DeliverySystemVerilog, plain-text, unencrypted — full visibility and portability
LicensingFlexible licensing model suited for small-scale to large-scale SoCs
Ecosystem IntegrationDeep integration with IDesignSpec for register maps, connectivity, and bus IPs
Target Applications
Multi-Core Processors
Scalable communication between CPU clusters, caches, and memory controllers
Edge Computing
Compact, power-efficient NoC for embedded AI and edge inference SoCs
Aerospace & Defence
Reliable, certified interconnect fabric for mission-critical and safety-qualified designs
Automotive SoCs / ADAS
ISO 26262-ready interconnect fabric for safety-critical autonomous driving platforms
Networking & Comms SoCs
High-throughput packet routing for 5G, networking, and protocol processing chips
Data Center Accelerators
Scalable interconnect for cloud AI chips and custom ASIC accelerators
Industrial & Consumer Electronics
Flexible NoC for diverse SoC architectures across industrial IoT and consumer devices
Benefits
BenefitDescription
Faster Time-to-Market
Parameter-driven generation eliminates manual implementation of routers, network interfaces, and interconnect fabrics, allowing teams to rapidly create and iterate on NoC architectures.
Unlimited Scalability
Deploy as many NoC instances and Network Interface Units (NIUs) as required by your design.
Open and Portable RTL
Receive plain-text, unencrypted SystemVerilog RTL with full visibility and auditability.
Deadlock-Free Communication
Dedicated virtual channels and configurable arbitration simplify protocol management and improve reliability.
End-to-End Automation
Integrated with the IDesignSpec Suite for RTL generation, integration, verification, documentation, and sign-off collateral generation.
Why Network-on-Chip?
Traditional interconnects become increasingly difficult to scale as SoCs grow in complexity.
IDS-NoC provides:
- Improved scalability for large heterogeneous multi-core SoCs
- Reduced wiring congestion and simplified floorplanning
- Better timing closure through distributed communication paths
- Efficient support for high-bandwidth AI and accelerator workloads
- Flexible integration across processors, memories, and peripherals
Resources
- IDS-NoC Product Datasheet (PDF)
- AXI4-Based NoC: A Scalable Interconnect Solution for Modern SoC Design (Whitepaper)
- IDesignSpec (IDS-GDI) Product Overview
- Request a Live Demo or Talk to an Expert
Build the Next Generation of Scalable SoCs
Automate NoC design, integration, and validation with Agnisys IDS-NoC
What Our Clients Say
Eugin Liu, R&D Vice President
iCatch Technology
"Integrating IDS-Integrate into our design workflow allows us to automate complex SoC assembly tasks, reducing manual errors and accelerating our development timeline. This aligns with our commitment to delivering high-performance, cost-effective solutions to our customers–particularly in the development of our ThetaEyeTM AI solution SoC through our Vision-ASIC design services model".
Joon Kim, Director of TPM
Etched
"With Agnisys’ IDesignSpec, we have a powerful tool that automates our specification-driven workflow, allowing us to work more efficiently and eliminate risks associated with manual processes”.
Yukio Watanabe, IC Expert at Wacom
Wacom
With Agnisys as a trusted EDA partner. We look forward to reducing our overall IP and chip risks and speeding quality products to market for our eagerly awaiting customers.
Build the Next Generation of Scalable SoCs
Automate NoC design, integration, and validation with Agnisys IDS-NoC-Gen
