IDS-AI Suite - Golden Specification to CSR Sign-Off
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IDS-AI Suite

Specification to Signoff with Agentic AI

Agnisys IDS-AI Suite is the industry's first agentic AI framework that understands semiconductor design intent and drives the entire development flow—from golden specification creation to RTL sign-off. Built on top of Agnisys' automation platform — perfected over the last two decades, it combines certainty and accuracy of Agnisys tools with reasoning and productivity of AI.

Design Smarter. Verify Faster. Reach Sign-Off with Confidence.
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Inputs

Markdown
Text
HTML
PDF
Word
Self-correction loop

SoC/IP RTL

Verification (UVM Tests)

Validation (Environment & Tests)

Integration (SoC Assembly)

Documentation

Sign-Off

Enable First-Silicon Success
Root cause of ASIC and FPGA functional flaws*
~45%

of ASIC functional flaws trace to incorrect or incomplete specifications.

~30%

are caused by changes to the specification.

14%

of ASIC projects achieve first-silicon success.

IDS-AI
100%

CSR verification coverage at sign-off.

* 2024 Wilson Research Group Study by Siemens EDA

Why Specification Matters

The design specification is the single most important creation in the Chip development process. Incorrect or incomplete specifications become the root cause of ~45% of the functional bugs, further, changes to specification become the source for another 30% of bugs*. Those numbers are worse for FPGAs (close to 60% and 40% respectively).

For ASIC projects, only 14% have first-silicon success*.

Source: Siemens EDA / Wilson Research Group 2024 functional verification trend reports: IC/ASIC report and FPGA report.

Root cause of ASIC and FPGA functional flaws*
80% 60% 40% 20% 0% DESIGNERROR INCORRECT /INCOMPLETE SPEC CHANGES INSPECIFICATION INTERNALIP FLAW EXTERNALIP FLAW ASIC FPGA Multiple responses possible

The 1/10/100 rule is a quality management principle which states that the later a defect is discovered, the more expensive it becomes to fix. Finding the bug in specification and having a correct and unambiguous definition of the functionality is the best way to develop a chip. This is the exact purpose of IDS-AI.

IDS-AI is an intelligent layer on top of the correct-by-construction Agnisys tools that have been perfected over the last two decades.

Cost curve: illustrative 1 / 10 / 100 defect-cost heuristic, shown separately from the Wilson verification-study data; see AKF Partners and Perforce summaries of the rule.

The 1 / 10 / 100 rule
$1 $10 $100 $1M+ Specificationphase RTL / architecturephase Implementation /verification Silicon / post-siliconphase Find defects in the specification, where they are least expensive to fix.

One Intelligent AI Layer Across the Agnisys Platform

IDS-AI is built around an agentic AI engine that works across the Agnisys platform. Instead of interacting with a separate AI assistant for each tool, engineering teams work with one intelligent assistant that understands golden specifications, design intent, CSR verification requirements and Integration flow.

The AI coordinates the underlying Agnisys tools automatically to carry out complex engineering tasks with minimal manual effort.

IDS-AI is also AI-platform agnostic: teams can use Agnisys' built-in platform — with IDS-CF as the harness — or plug in a platform of their own. It supports both on-site and remote usage.

What's Inside the IDS-AI Suite

The IDS-AI Suite brings all Agnisys tools under one framework, including:

Golden specification Design intent and CSR requirements
IDS-AI
IDS-GDISpecification and design intelligence
IDS-VerifyVerification automation
IDS-IntegrateIP and RTL integration
IDS-BatchBatch execution and automation
Additional toolsAdditional Agnisys automation tools
IDS-CF · Common Agentic AI frameworkSpec Check · CSR Sign-off · 100% CSR verification coverage

All operating under a common Agentic AI framework, with capabilities such as Spec Check and CSR Sign-off (100% CSR verification coverage) built directly into IDS-CF.

Describe the required behavior or deliverable in natural language. IDS-AI can ground the request in data sheets, legacy headers, tables, and engineering notes.

Convert the request into structured, checked, and versioned design intent. The golden specification remains the source of truth for every downstream action.

Run the correct Agnisys generators to produce synchronized RTL IP, RTL SoC, UVM/RAL, headers, IP-XACT, documentation, and validation assets.

Compare generated artifacts with the golden specification, identify conflicts or drift, correct the source, and rerun only the affected handoffs.

Complete the flow with synchronized artifacts, traceable results, and 100% CSR verification coverage tied to the final approved specification.

Key Agentic AI Capabilities

Specification Creation & Intelligence

Accelerate specification development with AI-powered creation, verification, validation, and a self-correcting loop that continuously improves specification quality by detecting and resolving issues automatically.

  • Create and manage functional specifications, including CSR specifications and sequences, in a collaborative environment using intuitive text-based and graphical interfaces.
  • Analyze specifications for completeness, correctness, and integrity.
  • Detects and automatically resolves inconsistencies between specifications and CSR definitions.
  • Automatically correct IDS-Batch-reported warnings and errors across supported specification formats, including SystemRDL and IDS-CF templates.

Create -> Generate -> Check -> Self-correct -> CSR Sign-Off

The sequence loops continuously: detect the conflict, correct the source, regenerate affected collateral, and close coverage.

Golden specification1 issue
block
reg
field
width8!
reset0x1FF!
swrw
hwro
IDS-AI execution tracequeued
0x1FF needs 9 bits; declared width is 8. IDS-AI corrects the golden specification and regenerates dependent outputs.
1 Detect conflictReset width and declared field width disagree. queued
2 Correct sourceGolden specification updates width from 8 to 9. queued
3 Regenerate collateralRTL, UVM, headers, and docs are refreshed together. queued
4 Verify closureCSR coverage resolves to 100% with clean artifacts. queued
Generated artifactsstale
RTL (IP)stale
RTL (SoC)stale
UVM / RALstale
Headersstale
Docsstale
CSR coverage72%
Loops while this section is in view.

Design & Integration Automation

Go from golden specification to implementation-ready design faster, with less manual RTL work and fewer integration errors — whether you're working with generated logic, existing IP, or hand-written RTL.

  • Generate implementation-ready RTL design directly from the golden specification.
  • Create and maintain connections to in-house and third-party IPs.
  • Assist with integrating generated RTL and manually developed RTL, ensuring that generated and user-created content remains synchronized and consistent.
  • Perform intelligent logic assembly and connectivity based on natural-language instructions.
IDS Collaboration Framework
Project context / redacted/spec_workspace
UUser
AAgent
Agent action plan and tool analysiswaiting
1.
ok ids_spec_check
Detected width/reset drift in redacted CSR block. Selected source correction in golden specification.
2.
ok ids_generate
Regenerated RTL IP, RTL SoC, UVM/RAL, headers, docs, and IP-XACT. Confirmed all generated artifacts are synchronized.
3.
ok list_directory
Captured output manifest, file sizes, and generated handoff report.
Files created - 0Preparing
/output/redacted/csr_signoff/
block_external_ids.sv3.5 KB
csr_agent_pkg.sv2.0 KB
Makefile.questa2.9 KB
ral_model.sv8.1 KB
handoff_report.html14.2 KB
6 more queued
CSR verification environment generated successfully

Location: output/redacted/csr_signoff/

FileSizePurpose
csr_agent_pkg.sv2.0 KBBus agent package
ip_registers.sv3.5 KBRTL IP handoff
soc_map.sv2.6 KBSoC integration map
Message... mention files, Enter to send

Verification & Sign-Off Automation

Reduce verification effort and accelerate sign-off through AI-powered automation that generates complete verification environments and ensures comprehensive CSR verification coverage.

  • Automatically generate verification testbenches and tests.
  • Generate validation environments and tests.
  • Achieve CSR sign-off with 100% RTL verification coverage.
  • Extend verification automation to full-chip verification, including user logic and application-specific functionality.

Consistent Output Generation

Generate implementation-ready collateral directly from the golden specification, including:

  • RTL Design
  • IP Integration Artifacts
  • Verification Testbenches and Tests
  • Validation Environments and Tests
  • Documentation
Explorer
8 filesregenerated together
output/redacted/ip_register_block.sv 8.3 KB - confirmed on disk

Synthesizable register RTL generated directly from the golden specification. Field offsets, reset values, access policies, and documentation references remain traceable.

Every generated artifact remains synchronized with the golden specification, providing a single source of truth throughout the development lifecycle.

The result is a streamlined, specification-driven flow that enables engineering teams to move from golden specification to sign-off faster, with higher quality and significantly reduced manual effort.

Benefits

Reduce Design Re-Spins

Catch specification defects before implementation begins.

Improve Engineering Productivity

Automate repetitive engineering tasks so teams can focus on innovation.

Accelerate Verification

Auto-generate verification environments and close coverage faster.

Improve Specification Quality

Maintain complete, correct, and consistent golden specifications throughout the project lifecycle.

Enable First-Silicon Success

Reduce costly design iterations and improve project predictability.

What Makes IDS-AI Different?

Unlike generic AI assistants, IDS-AI, the agentic AI framework coordinates multiple engineering tasks instead of answering isolated questions — delivering real engineering automation, not just a chat assistant bolted onto existing tools.

IDS-AI understands semiconductor design intent. It leverages the core Agnisys tools to generate correct-by-construction collaterals for Design, Integration, Verification & Validation and combines it with the power of agentic AI to catch and fix issues upfront in the ASIC development flow and remove the drudgery of design/verification engineers to produce signoff quality outputs.

Built For

AI Accelerators Automotive SoCs Data Center Processors Networking Chips Storage Controllers FPGA Platforms Embedded Systems Custom ASIC Development

Why Agnisys?

For over two decades, Agnisys has helped semiconductor companies automate specification-driven design. IDS-AI builds on this proven foundation, combining correct-by-construction automation with next-generation Agentic AI into one unified platform — for specification creation, design generation, verification, integration, and sign-off.

IDS-BatchGeneration engine for RTL, UVM/RAL, headers, IP-XACT, and documentation.
IDS-VerifyUVM environments, formal properties, and CSR verification assets.
IDS-IntegrateSoC-level connectivity, interconnect, and integration collateral.
IDS-CFCollaborative specification authoring, versioning, and the agent work surface.
Structured context in motion
01 Ingest 02 Resolve 03 Synchronize
Source / checked
Golden specification

Structured intent, CSR definitions, versioned source of truth.

IDS-Verify / checking
Verification assets

Generated tests and coverage trace back to declared behavior.

Agnisys logic core
Structural motion in progress
IDS-Batch / writing
Correct generators

RTL, UVM, headers, IP-XACT, docs, and integration outputs.

IDS-Integrate / synchronized
Integration flows

SoC connectivity and handoff collateral stay synchronized.

Ready to Transform Specification-Driven Chip Development?

See how the Agnisys IDS-AI Suite takes you from Golden Specification to CSR Sign-Off — faster, with higher quality and greater confidence.

Request a Demo Talk to an Expert Download Datasheet

What Our Clients Say

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