Introduction Modern System-on-Chip (SoC) designs are becoming increasingly complex as they integrate multiple processors, accelerators, memory subsystems, and peripherals. Ensuring […]
As register maps grow into the tens of thousands of fields, and design teams distribute across geographies, relying on
Many of you have probably heard the term “wheel of reincarnation,” which has its roots in Hinduism and Buddhism
Verification of modern IP and SoC designs presents several challenges. Specifications are often interpreted differently across teams, such as design
If you’ve worked with Zephyr RTOS, you already know that devicetree files are a core part of how hardware
In today’s semiconductor industry, the most interesting and challenging chips are embedded SoCs. I think it’s worth mentioning that
In my most recent blog post, I reminisced about childhood toys that let you construct complex structures from simple
As kids, many engineers enjoyed toys that involved assembling complex designs from simple elements. Whether it was wooden blocks,
As semiconductor designs grow exponentially in complexity, verification has become the single largest consumer of engineering time and resources.
IDS generates rich, interactive HTML documentation hosted within the Collaboration Framework (IDS-CF), enabling fast navigation, smart search, sorting, filtering, and
IDS generates DFT-aware RTL by introducing configurable control and observe points across critical logic such as read data, address decode,
As you may have seen, we publish quite a few blog posts here on the Agnisys site. We cover
As you may have gathered from my recent posts on related topics, artificial intelligence (AI) is very important for
As we begin the new year, we’d like to share a snapshot of the key enhancements delivered in the
Recently, I introduced Agnisys Collaboration Framework (CF) as a useful tool for managing your single source of truth (SST)
Recently, I wrote the blog post “Design, Verification, and Software Development Decisions Require a Single Source of Truth” and
You may have heard the phrase “single source of truth” sometimes abbreviated as “SSOT”—in the computing world. Although it
Discover how IDS-Integrate transforms System-on-Chip (SoC) development through intelligent automation. From hierarchical design and Git-aware version control to power,
There are countless challenges at every stage of system-on-chip (SoC) design. Just defining the overall architecture involves many iterations
How Engineering Teams Can Build Faster, Smarter & More Reliable Chips Chip design has always been a highly intricate process
I’ve been writing a lot about AI lately, but for some good reasons. AI seems to be dominating a
If you ask people what defines a system-on-chip (SoC) design, you’ll probably get one of three responses. Many contend
In today’s semiconductor industry, System-on-Chip (SoC) design has become increasingly complex. Modern SoCs integrate multiple intellectual property (IP) blocks,
Semiconductor development is one of the most dynamic industries in history. Change is constant, stemming from evolution in underlying
The Complete One-Stop Solution for Modern SoC Design Challenges In the fast-paced world of semiconductor design, enterprises need robust, flexible,
Introduction IDesignSpec (IDS) suite of products can seamlessly integrate into your Vivado projects allowing for faster turnaround times. IDS can
Join Agnisys for a technical deep dive into IDS-FPGA, a comprehensive solution that automates the end-to-end FPGA development process,
Hardware verification has always been the quiet bottleneck in chip development. For those working in the industry, it’s a
A recent blog post looked at the impact artificial intelligence (AI) is having on chip development, focusing on register-transfer-level
Taking IP Integration Efficiency to the Next Level Designing modern System-on-Chip (SoC) architectures continues to grow in complexity, particularly
If you search for the definition of CSR, you will likely find “corporate social responsibility” at the top of
The Challenge of IP Integration in SoC Design In modern System-on-Chip (SoC) design, integrating thousands of Intellectual Property (IP) blocks
Ever wondered how SoC design teams keep all their files in sync and avoid costly errors? Synchronization of files
The race to develop faster, more efficient AI chips is reshaping industries worldwide. As AI-driven applications surge in areas like
System-on-chip (SoC) projects, by their very nature, involve both hardware and software. Most people define an SoC as a chip
When looking at emerging and rapidly expanding technologies, it can be hard to separate the reality, the potential, and
Managing and visualizing register maps is critical for any chip design team. Complex IPs and SoCs demand tools that offer
As AI seems to be taking over the world, and AI chips seem to be taking over the semiconductor
Every semiconductor design starts with a specification, traditionally written in a natural language such as English. Every team—hardware, software, verification,
American statesman Benjamin Franklin is famously quoted as saying “in this world, nothing is certain except death and taxes.”
If I’ve been blogging a lot about artificial intelligence (AI) recently, there are several good reasons for this. Of course,
Over the years, there have been some seismic shifts in the semiconductor industry. Because of the huge quantity used
Every IP and chip design is created for one reason: to build a successful electronic product. This is true regardless
Developing a System-on-Chip (SoC) is a complex process involving multiple steps, iterations, and collaboration across diverse teams. From managing
System-on-Chip (SoC) development has become a cornerstone of modern electronic design, driving innovation across industries like automotive, consumer electronics, and
Abstract ISO 26262, derived from the IEC 61508 standard, is critical in ensuring the functional safety of automotive electronic and
Efficient management of registers and memory maps is critical for the success of modern System-on-Chip (SoC) designs. As SoCs
Introduction Usually, Any Digital Peripheral Custom IP is divided into two sections. One is designed logic circuits based on their
IDesignSpecTM (IDS) is a product suite that improves the productivity of FPGA/ASIC, IP/SoC, and system development teams. These products encompass
The Agnisys PSS (Portable Stimulus Standard) Extension in Visual Studio Code (VS Code) is an essential tool for hardware verification
The Agnisys SystemRDL Extension in Visual Studio Code (VS Code) is a powerful tool for hardware designers working with SystemRDL—the
The Agnisys IDesignSpec™ Suite provides comprehensive clock domain crossing (CDC) circuitry support for both hardware and software. Key synchronization
Agnisys IDesignSpec™ optimizes low power design through advanced clock gating. By disabling the clock for inactive registers, IDS reduces dynamic
IDesignSpec™ enhances system reliability in safety-critical applications with features like SECDED, which corrects single-bit errors and detects two-bit errors, preventing
Agnisys IDesignSpec™ facilitates seamless integration of various bus interfaces through automated generation of decoders and bridges, streamlining the design
IDesignSpec™ provides robust support for complex structures and register types, enabling engineers to define intricate designs with remarkable flexibility.
Agnisys IDesignSpec™ streamlines the design process by interactively generating comprehensive output files tailored for design, verification, software, and documentation teams. From
IDesignSpec™ empowers users with approximately 450 properties that enable extensive modification of the structure and behavior of generated outputs.
The Agnisys IDesignSpec™ (IDS) suite offers powerful support for reading third-party data in various formats, including industry-standard formats like
The Agnisys IDesignSpec™ Suite is certified for functional safety standards like ISO 26262 and IEC 61508, supporting all ASIL
Maintaining a single golden specification is essential for consistency in chip development. Traditional workflows often lead to synchronization challenges
Agnisys was founded on a deceptively simple idea: automatic generation of as many IP and system-on-chip (SoC) development files
There is probably no hotter topic in electronics right now than artificial intelligence (AI). AI was a fringe technology for
SystemRDL (System Register Description Language) plays an important role in the life cycle of System-on-Chip (SoC) development, facilitating efficient design,
Designing semiconductor devices has always been a distinct specialty of engineering, but today’s designers face immeasurably greater challenges. A typical
Introduction Assertion-based verification (ABV) is a powerful methodology used in modern hardware design verification. By embedding assertions within the design,
Alias Registers in RTL Design: An alias register is a hardware feature that allows multiple names or addresses that refer
Chip designers have always reused circuitry, when possible, to shrink the project schedule, save resources, and reduce risk by using
In SoC projects, where complex designs and architectures are the norm, having solid documentation is absolutely essential. It is important
In digital design, saving power is extremely important. It’s a top priority because it helps devices run efficiently. As electronic
Introduction In the ever-evolving landscape of technology and design, navigating through intricate documentation can often feel daunting. Recognizing this challenge,
The Universal Verification Methodology (UVM) has become a standard for verifying complex digital designs. One of the key components of
Introduction Agnisys has developed a Programmer’s Reference Manual (PRM) that serves as a comprehensive documentation resource for “programming sequences” and hardware
Introduction As our product portfolio has evolved over the last two decades, so has the capabilities of the various tools
SystemRDL (Register Description Language) is a language used for describing the register maps of digital systems, particularly in the context
IDesignSpecTM (IDS) is a product suite that improves the productivity of FPGA/ASIC, IP/SoC, and System Development teams. These products encompass
Introduction IP-XACT stands for Intellectual Property exchange-Advanced Configuration and Integration of IP components. It is an IEEE standard (IEEE 1685)
Register automation is an integral part of IP and SoC development. Long ago, design, verification, firmware, and documentation teams preferred
Introduction In the field of hardware verification, the Universal Verification Methodology (UVM) is a powerful framework that provides a systematic
SystemRDL, or System Register Description Language, is a specialized hardware description language (HDL) used for specifying registers in digital systems.
Introduction The IDesignSpec™ Suite by Agnisys stands as a versatile solution, simplifying the capture of hardware/software specifications in diverse formats
In the dynamic landscape of Very Large Scale Integration (VLSI) design, the ever-growing complexity of Application-Specific Integrated Circuits (ASICs) has
Formal verification is a crucial aspect of ensuring the reliability and safety of systems. ARV stands for Automatic Register Verification.
Agnisys is an Electronics Design Automation (EDA) company offering tools to automate specification to IP and SoC design and development,
Developing semiconductor intellectual property (IP), system-on-chip (SoC) designs, and complete systems is enormously challenging. Even a small error in the
As chips get ever larger and more complex, one thing is for certain: the electronic design automation (EDA) tools, techniques,
Modern system-on-chip (SoC) devices get more and more complicated each and every day. As the size and complexity of modern electronic
Late last year, I published a blog post that summarized what had transpired for Agnisys over the course of 2021.
The Intersection of Functional Safety and Electronic Design In an industry that has gone through an incredibly rapid transformation over
Register-transfer-level (RTL) code, formal analysis, RTL simulation, and logic synthesis have all raised the abstraction level of electronic design and
The Agnisys IDesignSpec™ Suite offers development teams a closely linked set of products, including a unified graphical design interface (GDI)
The UVM register model is an essential component of the UVM-based verification for modern designs. In this article, we discuss
In the ever-evolving landscape of semiconductor and electronic design, the pursuit of efficiency, consistency, and reusability remains paramount. Designers frequently
Agnisys offers a leading solution with comprehensive features to guarantee the accuracy of each semiconductor component right from the beginning.
UVM Register Model, a key component of the Universal Verification Methodology (UVM), is a standardized methodology for verifying digital designs.
In system design, engineers grapple with two formidable challenges: the relentless miniaturization of technology nodes and the ever-pressing demand for
In the ever-accelerating landscape of technological advancement, Agnisys has emerged as a trailblazer, reshaping the electronic design automation (EDA) industry
Introduction Engineers have consistently strived to expedite ASIC development. Our latest endeavor at Agnisys introduces automation that captures specifications in
As I noted in a recent post, registers appear everywhere in system-on-chip (SoC) design. Architecturally defined registers form the hardware-software
In the world of semiconductor design, where precision and efficiency are of utmost importance, the demand for streamlined methodologies is
The first and one of the most important steps of ASIC design flow is chip design specification. The specification can
Machine learning has begun to have a huge impact on the EDA Industry. Numerous organizations are heading forward with homegrown
Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher
In my last blog post, I talked a bit about the history of the annual Design Automation Conference (DAC) and
The two biggest challenges of today’s complex design are IP-Integration and Verification, and we would like to address solution scoping
The Large Hadron Collider (LHC) at CERN is the worlds largest and most powerful particle accelerator. This research facility enables some
Every year we take a look back at the resources we’ve created to determine what you’ve found most useful. We
We almost didn’t go to DAC this year, and that would have been a big mistake. Monday started out with
OK rockets are not taking off yet, but we are excited to launch a new capability for our IDesignSpec suite
As we transition into 2023, it’s a good time to look back over the past year and assess it, much
The electronics industry’s current state intensifies demands on design, verification, and validation teams, requiring them to achieve more with fewer
Wow, what a marvelous year 2015 has been to Agnisys, full of events at the various technical exhibitions, new customers,
So we have been working in the register specification space for a long time. We came out with the IDesignSpec
Machine Learning (ML) is the rage these days and we were not untouched by it. Being immersed in Specifications and
Somewhere in the deep trenches of a UVM-based verification project, an engineer teeters on the verge of insanity.
For decades, the idea of an open-source central processing unit (CPU) core was virtually unknown—let alone using it for commercial
Consolidation is not a new phenomenon for the semiconductor Industry. Although the industry has shown no consolidation through almost all
In my last post, I discussed the importance of partners to the EDA industry in general, and to Agnisys in
Improved technology for remote learning emerged as one positive outcome amid the challenges of the last year and a half.
Within the automotive sector, the safety of electrical and electronic systems (E/E) is mission-critical. As many of you likely already
There is something anticlimactic and tedious about interconnecting the hundreds or thousands of design blocks that make up a modern
By Louie De Luna, Agnisys Chief Product Evangelist
Hardware is verified using simulators. Software compiled and debugged using compilers and debuggers. When it comes to the hardware/software interface,
Has a chip ever been released that was entirely free of design errors? Not likely. While today’s design teams must
We all have different tastes and different habits and when it comes to work we like to work in different
I hope that you’ve been able to attend or watch the recordings of the sessions in our latest webinar series
Introduction With growing advancements in hardware designs, the complexity of designs has increased multiple folds and brought great challenges to
Navigating SoC Complexity System-on-chip (SoC) projects are, by their very nature, complex and difficult to complete successfully. Specification, architecture, design,
By Louie De Luna, Agnisys Chief Product Evangelist
While more registers mean more functionality and configurability, more is not always better.
Modern RTL design verification (DV) environments are both compelling and very complex. They include advanced simulation testbenches plus support for
We talk about the creation of complex registers in IDesignSpec and the generation of their suitable RTL and UVM models.
Regular readers of this blog know that Agnisys started as the first company to fully automate the design, verification, and
In February, we will celebrate the tenth anniversary of Accellera approving the first version of the Universal Verification Methodology (UVM).
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry.
Modern SoCs get more and more complicated every day. As the complexity of modern electronic semiconductor device design increases, niche
Introduction As per the IP-XACT User Guide, IP-XACT defines an API called Tight Generator Interface (TGI) to query, modify, create,
By Louie De Luna, Agnisys Chief Product Evangelist
Just about a year ago, I published a blog post about the emerging need for better functional safety and security
By Louie de Luna, Agnisys Director of Sales and Marketing
Moore’s law prediction about the increase in density of an SoC design continues to prove accurate with each advancement of
Typically thousands of registers are required for today’s complex designs, which are used to control the operations of the SOC.
It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal Verification Methodology
Register Generation is a Must-Have Capability Today’s SoC designs contain several thousands of registers and memory map elements. The design
There is probably no component more ubiquitous across integrated circuit (IC) and intellectual property (IP) designs than registers. Addressable registers
As regular readers know, Agnisys is the leader in specification automation. From various forms of executable design specifications, we generate
Verifying any large chip design is challenging, but a system-on-chip (SoC) presents additional requirements. By definition, an SoC includes one
I frequently delve into the solutions Agnisys offers for the seamless generation of design, SoC verification, testing, software, validation, and
A recent blog post noted that today’s RTL design verification (DV) environments are very powerful and very complex. The SystemVerilog-based
Over the last couple of months, I have discussed some key recent additions to the Agnisys solutions for system-on-chip (SoC)
Overview Electronics in general, and embedded systems in particular, become more critical every day. There is hardly a single aspect
In the realm of semiconductor development, often characterized by its pioneers, cowboys, shootouts, gamblers, and gunslingers, one might be tempted
A couple of years back at the Design Automation Conference (DAC), as I strolled through the exhibit floor, I
Most of us have faced difficulties in our personal and professional lives, and have worked our way through them. But
Agnisys just released DVInsight-Pro version 2.0 with many new features that enable much more productive SV/UVM code development. Do you
Ask a bunch of engineers about the Universal Verification Methodology (UVM) and you’ll hear two distinct sets of responses,
The last month has been busy for all of us at Agnisys, with three important virtual events. As I previewed
Introduction to IP-XACT IP-XACT is an IEEE standard, specifically IEEE 1685, providing a standardized XML schema for describing and
By Louie De Luna, Agnisys Director of Sales and Marketing
As we travel professionally, sometimes we tend to miss some of the scenery along the way. We can get a
As we close in on the final days of 2021, I can’t help but think back over the events of
Over the last few months, I’ve primarily shared two kinds of posts on this blog. The Design Automation Conference (DAC)
This was an intriguing DAC. Hardware-Software Interface (HSI) is increasingly emerging as an area of importance, and because of this
Participating in DVCon has always been a wonderful experience for us as an organization. We had a great response and
In a post last year, I discussed our recently announced Standard Library of IP Generators (SLIP-G™). This library has
Verification and Validation are two sides of the same coin
In my last post, I mentioned that Agnisys is currently in the middle of a series of new webinars
In my last post, I mentioned the three products we announced at the virtual Design Automation Conference (DAC) this
As an electronic design automation (EDA) company, Agnisys provides many benefits for chip design and verification engineers. Our specification
With the Design Automation Conference wrapping up this week in San Francisco, there is one thing we can say
It is penultimate day – the day before the big event! Preparing and launching the first ever DVCon India event
Important observations from Einstein and New England’s ice traders..
Agnisys will showcase IDesignSpec NextGen – the Next Generation product for capturing requirement specification for embedded designs, and automatically generating
After almost a decade of focusing on SV, UVM, SystemC to build software products and teaching advanced verification/modeling to hordes
The first day for exhibitors had lots of foot-traffic. Mostly casual onlookers, but a few who were genuinely interested in
As an EDA company our development cycle seems to revolve around DVCon and DAC. This year DVCon and DAC
I’m so excited … After years of work, my team and I have converted a word processor into an Engineering
As you know we have created a brand new EDA tool that saves people a lot of time and money.
Agnisys has customers designing all sorts of intellectual property (IP) blocks, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and
The DVCon Conference this year, was quite eventful for us with a lots of visitors at our booth. We were
Its heartening to see greater cooperation between various EDA companies, both big and small. The ongoing work under Accellera for
In our domain, we automatically generate registers and memory interface which can interface with all the standard bus protocols. If
DVCon 2014 was a wrap. It was marked by record attendance and participation both by the DV Community and
We had a great first day at DAC. All the talk about recession and economic doom were hard to believe.
Started blogging again, this time from our own blogging site.
System on Chip Design Challenges – The Highlight of DAC Day 2 It was a very busy day for Agnisys
The Design Automation Conference is over for the year. Attendee leads or inquiries, to be more precise, have been collected
Business schools teach us that the way to set the price on a product has nothing to do with the
Whether dealing with SoCs or a disaster in space, determining the correct set of steps is vital. No project
Here we go! The Design and Verification Conference (DVCON 2014) is round the corner. Make sure you register for the
Recently, I’ve been thinking about how vital partners are to the EDA industry in general, and for Agnisys in particular.
Most engineers involved in the design, verification, and validation of electronic systems are familiar with the Design Automation Conference (DAC).
The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course,
Anyone who’s worked in the EDA industry, and many of its customers, are aware of the annual Design Automation Conference
So the cat is out of the bag. We are working on an assertion tool. This DVCon we turned quite
Recently at the sidelines of DAC, Anupam Bakshi, CEO of Agnisys, Inc. sat down with Karen Bartleson, Director of
I feel like a bumblebee, going from the DVCon in US, to the next one in India to then
In engineering, we often go about our work not knowing how that work touches others’ life and society in general.
DVCon had a solid start in Bangaluru, India. The audited attendee numbers will be coming in later, but we believe
Published on 05-19-2013 07:30 PM in Semiwiki
Why Machine Learning Matters Machine learning (or “ML” for short) may have begun life as something of a buzzword, but
By Louie de Luna, Agnisys Director of North American Sales and Marketing
I’m thrilled. Finally, we have a customer who sees the value that IDesignSpec brings for his company. We are indeed
By Louie De Luna, Agnisys Chief Product Evangelist
By Louie De Luna, Agnisys Director of Sales and Marketing
I’m yet to meet a person who doesn’t like simplicity in engineering. I do believe that Electronic Design Automation (EDA)
Ending the last day of DAC strong with a presentation of DVinsight, a Universal Verification Methodology IDE The highlight of
IDesignSpec generates several outputs from a single spec. We started out as a simple tool that just dealt with registers.
The first day of the Design Automation Conference for Agnisys was exciting. We experienced a higher traffic flow than Monday
The input format of Duolog is now supported by IDesignSpec with outputs including Verilog, UVM, CHeader, and SystemC. The outputs generated
1981 marked the beginning of EDA as an industry. Within a few years there were many companies specializing in EDA,
I admit it, I get a high when meeting customers and hearing how they are using our tools. It is
Hardware design verification consumes more than 60% of resources, often more than that. These resources are not just engineers but
San Francisco, CA. June 2nd, 2014 – Agnisys, Inc. Launches DVInsight™, an Integrated Development Environment (IDE) for creating SystemVerilog (SV)
When engineers discuss system-on-chip (SoC) designs, they’re almost always talking about embedded systems with both hardware and software content. In
In our first Newsletter of 2022 we are drawing your attention to new capabilities in the IDesignSpec family of products.
Happy New Year 2021 to you all !!! With the new year, Agnisys tools have an amazing set of enhancements.
In this newsletter, you will find articles about the basic differences between Paged registers and Alternate register, Auto-Mirroring for volatile
