As we begin the new year, we’d like to share a snapshot of the key enhancements delivered in the Agnisys IDS Suite during 2025, focused on scalability, verification efficiency, and SoC integration for complex AI and high-performance designs.
IDS Suite 2025 – Highlights
- RTL & CDC Enhancements
Improved RTL generation with enhanced CDC support, parity and SECDED protection, optimized error handling, and advanced register and regfile capabilities. - Verification & UVM Improvements
Automatic generation of verification-ready environments, enhanced UVM RAL support, user-defined callbacks, and tighter RTL–verification alignment. - Design for Testability (DFT)
DFT-aware RTL generation with control and observe points to reduce ATPG complexity and improve debuggability. - IDS-CF – Collaboration Framework:
Enables cross-team collaboration through a shared, specification-driven workflow with traceability, controlled access, and an integrated HTML Viewer for improved visibility and alignment. - Advanced Documentation & IDS-NG Enhancements
High-performance HTML documentation, improved access through IDS-NG GUI, customizable templates, and automated license check-in/check-out. - IDS-Integrate & SoC Assembly
Enhanced IP-XACT support, flexible bus connectivity, mirrored interfaces, support for mixed bit-widths, improved SystemVerilog interface handling, and connectivity assertion generation. - Expanded IP Portfolio
Added and enhanced fully verified bus bridges, crossbars, protocol converters, and interconnect IPs, seamlessly integrable using IDS-Integrate. - AI² – AI-Powered Verification
Introduction of AI² for intelligent test generation, coverage analysis, and predictive debugging—reducing verification effort and time-to-closure by up to 70%.
These enhancements are designed to help teams handle larger, more complex SoC and AI designs while reducing manual effort and accelerating time-to-market.
Webinars Conducted in 2025
- Optimizing Hardware Design with SystemRDL: Tools, Techniques, and Tips
- AI Chip Design Using Agnisys
- Advantages of using IP-XACT and TGI for SoC Development
- Accelerating FPGA Development from Specification to System Validation with IDS- FPGA
- Top 5 Design Automation Techniques for AI Chip Development
Top Articles Published in 2025
- https://www.agnisys.com/blog/putting-all-the-pieces-together-with-ids-integrate/
- https://www.agnisys.com/blog/system-on-chip-design-integrating-complex-systems-into-a-single-silicon-solution/
- https://www.agnisys.com/blog/from-rigid-to-agile-make-the-shift-from-open-source-to-agnisys-idesignspec/
- https://www.agnisys.com/blog/agnisys-the-ai-chip-enabler/
- https://www.agnisys.com/blog/using-idesignspec-to-help-build-an-ai-chip/
We look forward to continuing our collaboration in 2026. Please feel free to reach out if you’d like a deeper walkthrough of any of these features.
