Clock Domain Crossing Circuitry Generation
The Agnisys IDesignSpec™ Suite provides comprehensive clock domain crossing (CDC) circuitry support for both hardware and software. Key synchronization […]
October 14, 2024
Low Power Design Generation
Agnisys IDesignSpec™ optimizes low power design through advanced clock gating. By disabling the clock for inactive registers, IDS reduces dynamic
Special Functional Safety Features
IDesignSpec™ enhances system reliability in safety-critical applications with features like SECDED, which corrects single-bit errors and detects two-bit errors, preventing
Bus Interface, Decoder, Bridge IP provided for APB®, AHB®, AXI®
Agnisys IDesignSpec™ facilitates seamless integration of various bus interfaces through automated generation of decoders and bridges, streamlining the design
Complex Structures & Complex Register Types
IDesignSpec™ provides robust support for complex structures and register types, enabling engineers to define intricate designs with remarkable flexibility.
RTL, UVM and C Model & API Generation
Agnisys IDesignSpec™ streamlines the design process by interactively generating comprehensive output files tailored for design, verification, software, and documentation teams. From
Most customizable and configurable outputs
IDesignSpec™ empowers users with approximately 450 properties that enable extensive modification of the structure and behavior of generated outputs.
IP-XACT, SystemRDL, Excel, Word, CSV, JSON, YAML, XML imports
The Agnisys IDesignSpec™ (IDS) suite offers powerful support for reading third-party data in various formats, including industry-standard formats like
IDesignSpec is ISO 26262 Certified product suite
The Agnisys IDesignSpec™ Suite is certified for functional safety standards like ISO 26262 and IEC 61508, supporting all ASIL
The best golden specification solution
Maintaining a single golden specification is essential for consistency in chip development. Traditional workflows often lead to synchronization challenges
