lp header

Agnisys Careers

Thank you for your interest in a career at Agnisys. 

Please review the job opportunities listed below and apply for the ones where you are qualified and you have the most interest.

 

pioneers-1

Hardware Design Engineer Trainee (Location: Noida, India)

Agnisys is looking for freshers to join our team to work on high tech products for the Semiconductor industry.

Agnisys is a leader in automating SoC development. It’s products are considered to be the most comprehensive and best in class. We offer a progressive, innovations-driven, learning environment. Don’t get pigeonholed into one specific area when you can learn the intricacies of Design, Verification, Firmware and overall chip design all at one company! Not only that, you will be exposed to Product Validation, Customer Support and an Agile development environment.

Agnisys focuses on research and development by participating in Accellera Systems Initiative, presenting in worldwide conferences, encouraging creative thinking and initiative.So if you value innovation and creativity and want to create a strong foundation for your career, join Agnisys today.

Basic Requirements: 

  • Candidates should be B.Tech.CS & MCA freshers/graduate

  • Basic Knowledge in Verilog, VHDL, SystemVerilog & C

  • FPGA, EDA Tools, Linux, Perl, Python, Tcl, Bash scripting

  • Should have excellent communication skills

  • Ability to work independently with little supervision as well as ability to work within a team

  • Excellent multi-tasking skills

  • Self-motivated with strong team spirit

Apply Now

 

Java Developer (Job Id: JD01, Location: Noida, India)

Agnisys is looking for experienced Java professionals. If you want to work on High-Tech semiconductor products, join the Agnisys Team.

Basic Requirements :

  • 3-4 years’ experience in Java development

    Graduate or Postgraduate from a good university

  • Strong algorithmic skills

  • Ability to work independently with little supervision

  • Excellent multi-tasking skills

    Self-motivated with strong team spirit

  • Candidate must have a high intelligence and emotional quotient

Job Description :

  • Create the next generation Electronic Design Automation software for Semiconductor companies

  • Understand the architecture of the current products and help in improving them

  • Expert level knowledge of Core Java, Data Structures, Compiler, Parser, XML is a must

  • Knowledge of HTML 5, CSS, JQuery, Parsers & XSLT

  • Use good coding practices for development – OOPs, JUnit, CoCo, latest Java features.

Apply Now!

DFT (Design for Test) Engineer– ASIC

Job responsibilities:

  • Has worked on scan-stitching; and has good knowledge of Scan-stitching related concepts.

  • Has worked on MBIST implementation and is confident with the Tessent flow of mbist-insertion.

  • Has worked on ATPG; and is well-conversed with the files required to run

  • ATPG. Knowledge and experience with Tessent ATPG (mentor) is a plus

  • Has worked on Spyglass-Lint.

  • Knowledge of automation scripts is a plus.

  • Knows the basics of JTAG & IJTAG.

  • Support Spyglass debug and coverage co-relation.

  • Support scan-stitching runs. Debug DRC other scan-related issues

  • Support ATPG. debug ATPG issues. debug coverage holes.

  • Support MBISTBISR insertion. debug insertion issues verification issues

  • Support gate-level simulations.

  • Job Types: Full-time, Regular / Permanent

DFT Engineer

Skill Set Requirements:

Full-chip DFT working experience with multiple design Tape Outs Block level and Chip level SCAN insertion, DRC, Coverage Analysis, and improvements.

Expertise in Scan Compression (EDT/OPMISR+), MBIST, BSCAN, ATPG implementation, and
verification.

Hands-on Experience with industry standard DFT EDA tools & flows (Tessent, Synopsys, Cadence)
Good Knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraints
developments & LEC.

Excellent problem-solving and debugging skills. Proactive in nature.Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
Leading junior teams, Mentoring/Training, and

Project leadership.

Excellent Customer interaction, Communication, and Teamwork skills Skills & Experience

ATPG (at-speed & stuck-at), Automatic Test Pattern Generation (ATPG), Design for Testability (DFT), Design Rule Checking (DRC), Formal Verification, Gate Level Simulation, Hardware Description Language (HDL), Test Pattern Generators

Job Types: Full-time, Regular / Permanent

Benefits:

Health insurance

Schedule:

Day shift

Supplemental pay types:

Performance bonus

Ability to commute/relocate:

Bangalore, Karnataka: Reliably commute or planning to relocate before starting work (Required)

Education:

Bachelor’s (Preferred)

Experience:

total work: 1 year (Preferred)

Apply Now!

Physical Design Lead/Manager

Full Job Description:

Experience with complete Physical Design Flow from RTL to GDS

FCFP, FCT, Clocking, Constraints, Synthesis, Timing Closures, FM, VSI, IR Drops, Low Power, FCFP along with Physical Design / Floor Plan, P&R

Experience with Synthesis & Hierarchical design is a plus

Experience in taping out in 5nm, 7nm, and 16nm multiple technologies

Expertise in floor planning large blocks or chip

Experience with Cadence Innovus, Synopsys ICC2, Prime-Time, Calibre

Scripting experience in Tcl, and Perl is a must

Involvement in flow development is a plus

Job Types: Full-time, Regular / Permanent

Benefits:

Health insurance

Schedule:

Day shift

Supplemental pay types:

Performance bonus

Ability to commute/relocate:

Bengaluru, Karnataka: Reliably commute or planning to relocate before starting work (Required)

Education:

Bachelor’s (Preferred)

Experience:

total work: 5 years (Required)

 

ASIC Design Verification Lead

Full Job Description:

1. You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.

2. Architect and Develop block level verification environments for sub-system and full-chip using System Verilog and UVM methodology.

3. Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity.

4. Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage, and Gate level simulation.

5. Develop Perl, Python, and/or shell scripts to improve current verification infrastructure/methodology.

Required Skills:

1. Desired experience: 4 years in real-time projects

2. ASIC Verification using System Verilog

3. Experience in constrained-random verification is a strong plus

4. Experience with verification methodology like OVM/VMM/UVM

5. Perl/Tcl scripting is strongly preferred

6. Strong problem-solving and ASIC debugging skills

Job Types: Full-time, Regular / Permanent

 

Talent Acquisition Specialist

Understanding the job description for assigned positions.

Sourcing, Screening & Shortlisting profiles through various sources like References, Social Networking Sites, databases, and Job portals w. r. t. the requirements.

Scheduling Interviews and coordinating with candidates and Panel.

Actively involved in POFU (Post Offer Follow Ups).
Maintaining daily/weekly/monthly reports and database for further assistance.

Job Types: Regular / Permanent, Full-time

Benefits:

Health insurance

Schedule:

Day shift

Supplemental pay types:

Performance bonus

Ability to commute/relocate:

Bangalore, Karnataka: Reliably commute or planning to relocate before starting work (Required)

Education: Bachelor’s (Preferred)

Experience: 2 years (Preferred)

Industry background : Semiconductors or B.tech with EC

Language: English (Required)

 

DFT Engineer

Full Job Description

Experience in complex SOC-level DFT execution in advanced finFET technology.

BSEE or MSEE with at least 2+ years of DFT experience in high-complexity SoC designs.

Strong DFT fundamental knowledge from defective models to ATPG algorithm

Deep knowledge of EDA tools such as Synopsys Tetramax or Mentor Tessent

Knowledge of basic SoC architecture and HDL languages like Verilog to be able to work with logic design teams for timing fixes.

Must possess good communication skills, be self-driven, and be a good team player.

Job Types: Regular / Permanent, Full-time

Benefits:

Health insurance

Schedule:

Day shift

Supplemental pay types:

Quarterly bonus

Ability to commute/relocate:

Bangalore, Karnataka: Reliably commute or planning to relocate before starting work (Required)

Education:

Bachelor’s (Preferred)

Experience:

total work: 2 years (Preferred)

Application Engineer

Milpitas, CA 95035
Full-time

Full Job Description
Agnisys is looking for Application Engineers for its fast-growing EDA tool user base.

Basic Requirements

· Minimum 2 years’ experience required

· The ideal candidate must have proven industry experience. Some travel may be required.

· Must have experience in large verification projects with a large team of people.

· System Verilog, SVA

· Verification methodologies primarily using UVM

· Bus protocols such as AMBA-AXI, AHB, APB, I2C, SPI

· Design/Verification of IP and SoC

· Fundamentals of computer architecture or practical experience of working on microprocessor designs

· Formal, Constrained Random, Emulation

· Industry standards like SystemRDL, IP-XACT, PSS and EDA tools like IDesignSpec

· Candidates must be eligible to work in the United States with relevant visa

Job Description

· Work with customers and understand their needs and provide solutions

· Develop and conduct demos and training

· Coordinate with R&D, Marketing and Sales teams

Job Type: Full-time

Benefits:

Health insurance

Experience level:

2 years

Schedule:

8 hour shift
Day shift

Ability to commute/relocate:

Milpitas, CA 95035: Reliably commute or planning to relocate before starting work (Required)

Work Location: One location