The Portable Test and Stimulus Standard defines a specification for creating a single representation of stimulus and test scenarios, usable by a variety of users across different levels of integration. With this standard, users can specify a set of behaviors, from which multiple implementations may be derived.
- PSS has constructs for
- Modelling Data flow (Buffers, Streams, States)
- Modeling Behavior (Actions, Activities, Components, Resource, Pooling)
- Constraints, Randomization, Coverage
- PSS is useful for SoC high-level test scenario creation
A concept of defining Registers and Sequences has been introduced in PSS2.0. Currently, three accesses are supported i.e., Read-Only, Read-Write, and Write-Only.
IDS-Validate helps in generating the PSS register model through various inputs supported by IDS such as SystemRDL, IP-XACT, IDS-NG, Word, Custom CSV, etc.
Steps for Generating PSS Register model using IDS-Validate
Use Case
IDS-Validate is a tool that helps verify the functionality of complex systems by creating and managing models of the hardware registers. These models regulate how the system interacts with the programmable registers in the hardware.
When testing a system, it's important to ensure that the system reads from and writes to the hardware registers correctly. IDS-Validate uses the supported input from the system to generate a model called the PSS Register model. This model defines the rules for accessing the registers.
The PSS 2.0 LRM core library provides a set of tools and functions (APIs) to control how the system accesses the registers and allows for modeling of the registers. These tools help in creating and maintaining the PSS Register model.
One of the features of IDS-Validate is the generation of C code equivalents of PSS sequences. These C-based testbench environments can be used for various purposes like testing CPUs or checking embedded systems. This allows for more flexibility in testing and verification.
IDS-Validate also focuses on reusability and scalability. It enables efficient verification of complex systems by providing a model-based approach. The PSS Register model and the automated test generation make it easier to verify and test large systems. This scalability allows the tool to handle sophisticated verification tasks effectively.
Example
Input SystemRDL Register Specification:
addrmap block1{
reg reg1 {
field {
sw=rw;
hw=rw;
}f1=0;
};
reg reg2 {
field {
sw=rw;
hw=rw;
}f1=0;
field {
sw=rw;
hw=rw;
}f2[31:15]=0;
};
reg reg3 {
field {
sw=rw;
hw=rw;
}f1[31:0]=32'h10;
};
reg1 reg1;
reg2 reg2;
reg3 reg3;
};
Steps for Generating Firmware and UVM sequence Output using IDS-Validate.
Sequences are a “set of steps” that involve writing/reading specific bit fields of the registers in the IP/SoC. These sequences can be simple, or complex involving conditional expressions, an array of registers, loops, etc. PSS users can write a single sequence specification and a compiler has been written to generate the UVM sequences for verification, System Verilog sequences for validation, C code for firmware and device driver development, and various output formats for Automatic Test Equipment.
This provides a solution for firmware engineers to write and debug their device drivers and application software. Consequently, PSS helps in the solution for SOC/IP teams who aim to cut down the verification and validation time, through automatic generation of UVM and sequences which enables exhaustive testing of memories and register maps.
This approach also unifies the creation of portable sequences from a golden specification. Sequences can be captured in PSS, python, spreadsheet format, or GUI(NG) and generate multiple output formats for a variety of domains:
- UVM sequences for verification
- System Verilog sequences for validation
- C code for firmware and device driver development
- Specialized formats for automated test equipment (ATE)
- Hooks to the latest Portable Stimulus Standard (PSS)
- Documentation outputs such as HTML and flowchart
The sequence constructs include loops, if-else, wait, and switch statements to change the interfaces, specify encoding formats, deal with time-unit differences, use macros, specify variants, and use return statements to return user errors from sequences. The constructs support constrained variables for randomized sequences and handling of indirect and interrupt registers.
Input PSS sequence Specification:
Example
Input PSS Sequences
Figure 1
Generated Firmware Sequences
Figure 2
Generated UVM sequences
Figure 3
Steps to Start Using
If you already have IDS, get a license for IDS-Validate. The command to use is Agnisys PSS Compiler or apc.sh and you can generate several outputs from it.
% apc.sh <input file> -out “<desired_output>” -dir <output dir>
APC(AGNISYS PSS COMPILER/EDITOR)
We are excited to introduce the latest update to our software, which includes the integration of a dedicated PSS (Portable Stimulus and Test Language) Editor. This new addition enables you to work with PSS files, create and edit portable stimulus models and tests with ease and ensures a seamless experience for engineers and testers working with this industry-standard language.
Key Features:
- PSS File Management: The PSS Editor allows you to efficiently manage your Portable Stimulus and Test Language files. Create new PSS files, open existing ones, and organize your project resources in a user-friendly interface.
- Syntax Highlighting: Enjoy syntax highlighting and code formatting that makes writing and reviewing PSS code more intuitive and error-resistant.
- Code Navigation: Easily navigate through complex PSS files with features like code folding, context-aware code suggestions, and jump-to-definition functionality.
- Validation and Semantic checks: Utilize built-in validation and debugging tools to ensure your PSS models and tests adhere to industry standards and functional requirements..
- Search and Replace: Quickly find and replace elements within your PSS code, improving code maintenance and efficiency.
If you wish to install and use the tool, download and install it directly from the Visual Studio Code (VS Code) Marketplace and Follows the instruction given in README.md
https://marketplace.visualstudio.com/items?itemName=AgnisysInc.agnisysPSS
Conclusion
IDS-Validate is a powerful tool that simplifies the verification of complex systems by creating and managing models of hardware registers. Generating the PSS Register model based on the system's input ensures correct interaction with the programmable registers. With the support of the PSS 2.0 LRM core library, the tool provides tools and functions for modeling and controlling register access. By automating test generation and facilitating reuse, IDS-Validate saves time and effort in system verification. The ability to generate C code equivalents of PSS sequences adds flexibility to the testing process. Overall, IDS-Validate enhances reusability and scalability, making it an effective solution for the verification of sophisticated system-level designs. PSS compiler and GUI generator have been developed for the generation of various outputs from the above golden custom sequence specification such as:
- System Verilog/MATLAB output for Validation
- UVM output for Verification
- C output for Firmware
- CSV output for ATE
- HTML/Flowchart for documentation
PSS editor enables you to work with PSS files, create and edit portable stimulus models and tests with ease, and ensures a seamless experience for engineers and testers working with this industry-standard language.
