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Agnisys makes Design Verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality. The The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized. Register Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!

Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible. “The  The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs. “IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”Automating creation of registers and sequences
How does the IDesignSpec automate the creation of registers and sequences across hardware and software teams?
Bakshi said: “The IDesignSpec uses templates to capture the data and additional properties from the user. These templates are smart, in the sense that they are content aware. If the user makes a mistake in specification, the templates catch that and notify the user. This ensures that the user does not produce bad outputs. This feature has single handedly avoided numerous bugs from creeping into the design.” There are about a 100 checks that are made on the specification document. Changes to the spec can be numerous and unordered, and yet, IDesignSpec can always produce consistent outputs. The checks are not just for the front-end design, but also for all the outputs that will be produced from the spec. The spec can be converted into a usable code for any of the outputs supported by IDesignSpec or any of the Tcl based user outputs. Register data is transformed into a variety of outputs which accurately represent the spec in the target domain such as: Synthesizable Verilog, VHDL, register models for Verification such as UVM, OVM, eRM, VMM, C/C++ code for Firmware, Standards such as IP-XACT, SystemRDL, and Documentation such as HTML, XML etc. Sequence data is transformed into UVM and Firmware Sequences that can be used by the verification and device driver teams, respectively. IDesignSpec helps in assertions in logic verification in the sense that the assertions are created automatically from the constraints. IDesignSpec also bring an innovative approach to capturing hardware control and status registers. The innovation is in the way the data is captured in an intuitive Word or Excel editor. Agnisys has two patents for the same. “The fact that no separate GUI is used means that a user does not need to learn a new GUI. The user is free to add additional information about the registers. Normally, the registers form a chapter in the functional spec. IDesignSpec enables the users to add that chapter in an executable form,” he added.

Enter spec and register information in single ‘live’ document

IDesignSpec is claimed to be the ‘only tool that enables users to enter both, the specification and the register information in a single ‘live’ document.’ Elaborating, Bakshi said: “Yes, it is the only tool in the world to use MS Word in this manner. A user enters the register data and its associated properties in Word (or Excel) and the data is indistinguishable from the regular information in the spec. Other tools require the users to click numerous times and enter the same data repeatedly. IDesignSpec enables users to easily and intuitively cut-copy-paste data as they would in a normal editor.” Register and Sequence data is embedded in the functional specification document – where it rightly belongs. Other tools require that this data is kept in some file or database external to the functional spec. In IDesignSpec, a “single source” is maintained for all related data. The user can enter images, tables and similar artifacts to be clear in the intent. Often, the intent is not clear in the spec. With IDesignSpec, the register and sequence data is specified in unambiguous form with leads to virtually zero defects in creating the spec, he added.
Presence at DAC 2013 Agnisys is partnering with all of the major EDA vendors. It is a Synopsys In-Sync partner, a Cadence Connections partner and in Mentor Graphics’ Questa Vanguard program. A list of Agnisys’ customers include folks such as Allegro Microsystems, Compound Photonics, Conexant, Discretix Technologies, Icron, INPHI, Intrinsix, ITT/Exelis, John Deere, Lab126, Lieca, Mentor France, Mercury Computers, Microsoft, NASA, Raytheon, SEAKR, Stec Inc., Violin Memory Inc., Volcano, Wipro and Xingtera. Agnisys is participating at the forthcoming Design Automation Conference (DAC) 2013, booth #1543, to be held June 2-6 2013, Austin, Texas, USA. Stop by its booth to collect Agnisys’ DAC special – a full feature, free copy of IDesignSpec and IVerifySpec, and a couple of goodies for existing and potential customers.
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