The current state of the electronics industry is placing ever increasing demands on your design, verification, and validation teams to do more with less. For Agnisys, this further catalyzes our laser focus on helping you meet the burgeoning demands of your most critical projects. With business slowdowns in some sectors, we’re seeing layoffs and belt-tightening at many companies. Consequently, we know you’re feeling the escalating strain of project demands being further complicated by distribution across smaller teams with disparate needs.
To directly address these mushrooming pain points, we’re delivering specification automation solutions that replace resource-intensive manual processes, freeing up your engineers to focus on innovation and more value-added tasks. It’s precisely because we work so closely with our users that we know how much the right solutions can make all the difference.
Solving Real-World Problems in IP and Chip Development
At Agnisys, user support continues to be a high priority. Our EDA solutions have been defined and developed in concert with leading customers to solve real-world industry problems in intellectual property (IP) and chip development. We pride ourselves on the rapid and comprehensive support provided by our applications engineering team. This is where we have a real advantage over gorilla-sized software companies trying to support their sea of products addressing a broad range of problems.
Many of our leading-edge customers have shared their experiences with our solutions, demonstrating how we helped shrink schedules, save resources, and improve quality on their chip and IP projects. For further details, check out these case studies.
If you’ve recently visited our website, you’ve likely noticed further examples of our user-oriented mindset. We’ve completely revamped our site to highlight the benefits gained by different project teams with the adoption of our solutions.
On our home page – front and center – we list the types of files our solutions generate automatically from specifications, and identify which project teams can benefit from these files. Every file auto-generated by Agnisys solutions saves engineering time and effort, especially important in the current economic climate.
You’ll find that our solutions are now organized by project teams with a table clearly displaying which solutions are applicable to which teams. We’ve also dedicated pages to solutions for functional safety and FPGA developers.
Again, our intent is to be as specific as possible about who benefits from what, and how they benefit. We want to help you better understand how solutions from Agnisys can address – and solve – your real-world challenges.
Our pulldown menu continues to provide the details on each solution we offer, but we’ve added solution overview pages to provide more details on the files we generate and how they can be used. We’re striving to provide clear and visible answers to your most pressing problems. We listened closely to you, our users, on what you wanted to see on our site, and how you wanted it organized. The new iteration of our website was created to accommodate and support your needs and requests.
If you’re already one of our users or familiar with Agnisys, you’ll also notice some important changes to our solutions. We’ve consolidated our IDesignSpec (IDS) Suite, bringing together what’s used by the same teams and moving certain features to better address your needs. For example, support for FPGA design and verification is now part of our primary solution suite, given many FPGA developers need the same advanced features as their ASIC counterparts.
We’ve created applications (apps) for specific project teams, making it easy for our users, existing and potential, to determine which solutions are best based on your job function. For example, if you’re a verification engineer, we’ve made it clear you’ll want to take a look at our IDS-Verify app.
Agnisys Solutions
Check out our complete suite of solutions for semiconductor and IP development:- IDesignSpec GDI automates the design and documentation of your memories, register sets, registers, and register fields. It benefits your designers and technical writers while providing a common graphical front end and an interactive generation engine for all your teams.
- IDS-Batch CLI generates all the same files as IDesignSpec GDI, but in command-line mode so that your development process engineers can incorporate it in your scripts, Makefiles, and continuous integration/continuous deployment (CI/CD) flows.
- IDS-Verify benefits your verification team by automatically generating a complete UVM-based simulation environment for verifying all your registers and memories, including custom test sequences, and SystemVerilog Assertions (SVA) that can also be used in formal verification.
- IDS-Validate automates pre-silicon and post-silicon validation. It automatically generates C/C++ sequences that exhaustively test your memories and registers to benefit your validation engineers, bring-up lab team, and embedded programmers.
- IDS-Integrate automates the assembly of your IP and custom design blocks into a full chip, saving your integration team a great deal of tedious manual effort. It automatically generates bus bridges and other infrastructure needed to interconnect the blocks.
- IDS-IPGen automatically generates both standard and custom IP blocks for your design. It includes a flexible and customizable library of IP generators for commonly used blocks such as AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPU, Timer, and UART. For custom blocks, you can specify state machines and data paths, and then generate both design and verification code.
Our updated online presence and solution suite is based on extensive discussions with our users, their needed features, and which generated files are most useful for each team. My sincere hope is that you find everything much easier to understand, evaluate, and deploy on your toughest chip and IP projects.
You’ll also find we’ve modernized our site to reflect the latest industry opinions and preferences. We wanted to make the Agnisys website easy to navigate, visually pleasing, and your go-to resource for tackling existing and evolving complex chip and IP development challenges.
Agnisys at DVCon U.S.
If you’re in San Jose, California on February 27th through March 3rd, I hope you’ll join us at DVCon on Monday, from 9-10:30am for the Pushbutton Complete IP Generation workshop in the Oak room. Or, visit with us at booth 104 in the Exhibit Hall on Tuesday or Wednesday afternoon to view our solution demos. Be sure to take our quiz on SoCs and Embedded Systems for the chance to win a portable charger or a portable Bluetooth speaker. We’re looking forward to meeting with you, in-person, at this conference to gain an understanding of your needs and the chance to show you how we can help!
It's been our hyper-focus on your engineering challenges and your project success that drove our time, energy, and investment in the new website. As a result, we want to hear your feedback. What do you think? Have we succeeded in making it easier on you to identify and evaluate solutions to your most pressing problems? Is there any information missing that you’d like to see? Please let us know your thoughts at marcom@agnisys.com.
Thank you for checking out the latest at Agnisys. We urge you to keep your eyes on us as we keep our ears open and tuned-in to you, enabling us to deliver industry-leading streamlined automation solutions that meet your most demanding projects!
There are multiple causes for design errors, but some of the most common are related to the design specifications and how they are distributed and maintained throughout the product development lifecycle. Learn how to address this issue by reading The IC Designer's Guide to Automated Specification of Design and Verification, for Better Products. 