Design Verification Articles
AI-Based Sequence Detection for IP and SoC Verification and Validation
A couple of years ago at the Design Automation Conference (DAC), as I walked the exhibit floor I was amused by how many EDA vendors had jumped on the marketing bandwagon for artificial intelligence (AI) and machine learning (ML). Many company slogans, booth posters, and demonstrations claimed that AI/ML techniques had been incorporated into their products. Doubtless some of these claims were true, but for certain companies and product ...
Adopting New Methods For Faster Development Of RISC-V based SoCs
The growth of new technologies such as artificial intelligence, machine learning, Internet of Things (IoT), virtual/augmented reality and of course, the various technologies for the automotive industry has led to a new ...
Creating Test Sequences for RISC-V Cores and SoCs
By Louie De Luna, Agnisys Chief Product Evangelist The idea of an open-source CPU core was virtually unheard-of ten years ago – let alone using it for commercial applications. The CPU core has been the most critical ...
Most Popular Posts
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New Product Advances Productivity for SystemVerilog UVM Verification -
Creating Test Sequences for RISC-V Cores and SoCs -
DVCon India takes off! -
AI-Based Sequence Detection for IP and SoC Verification and Validation -
2015 Year End review – DV Challenges -
Adopting New Methods For Faster Development Of RISC-V based SoCs
The Ultimate Shift Left
Important observations from Einstein and New England’s ice traders.. Albert Einstein defined it well: “Insanity is doing the same thing over and over again and expecting different results.” I have come across several ...
2015 Year End review – DV Challenges
Wow what a marvelous year 2015 has been to Agnisys, with full of events at the various technical exhibitions, new customers, new features and new products and not to forget – new partnership. It would be unfair to say ...
New Product Advances Productivity for SystemVerilog UVM Verification
Agnisys just released DVInsight-Pro version 2.0 with many new features that enable much more productive SV/UVM code development.
DVCon India takes off!
DVCon had a solid start in Bangaluru, India. The audited attendee numbers will be coming in later, but we believe we had approximately 425+ delegates. That is truly amazing for the first year of the event! For me, it ...
Getting Ready for DVCon India 2014
It is penultimate day – the day before the big event! Preparing and launching the first ever DVCon India event feels like taxiing a plane down the runway, ready to take off. It is new; the design was replicated from ...