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Electronic Design Automation Trade Show Update – 52DAC

Overheard a lot of talk about “Shift Left” – which refers to the higher levels of abstraction leading to higher levels of productivity. I find that interesting as we at Agnisys have been doing this left shift since 2010. We are as left-shifted as you can get! Any more and we will be in the brain of the design engineer. You see, our tools capture the design intent in the form of a specification. This specification is then transformed into usable code.

DAC is a great time to meet current customers, and we met some. A few told us how they have made IDesignSpec as part of their reference flow. A few others came by and said they bought the tool for its UVM model generation capability but they were now also using its RTL generation capabilities. That meant we needed to get in touch with the IP managers in the various companies as they have a different process for qualification.

While we were at the DAC show one ASIC design customer asked us for proof that our generated design IP is compliant with the standard.  Although we performed exhaustive testing of our IP, we needed access to a third-party-generated VIP that could conclusively prove to the customer that indeed it was compliant.  Fortunately, the Verification Academy booth was adjacent to us and I met with Dennis Brophy and Jason Polychronopoulos. They were eager to help us since we are a long-time partner. We received the VIPs from Mentor Graphics. It took us two days to install them and integrate them into our UVM-based design verification and regression environment. Within a week after DAC, we were able to send proof to this very important customer that all was good with our IP, as we expected.

This incidence at 52DAC shows two things:

1. DAC is useful for networking and getting things done and,

2. a partner in need is a friend indeed.

We are thankful to Mentor Graphics for granting us access to their VIPs. In another blog, we will describe more details of our experience with the Mentor VIP.

New product announcements at 52DAC

This year we announced a new product called ARV – Automatic Register Verification. It is an independent product that helps the verification engineer by creating verification proofs for the hardware/software interface in the design. The tool comes in two flavors, ARV-Sim and ARV-Formal. The ARV-Sim tool uses simulators for the task and ARV-Formal uses formal. The ARV-Sim accepts any of the standard textual formats like SystemRDL, IP-XACT, Custom CSV/XML, or our popular user-friendly formats for Word and Excel. It then generates the complete UVM-based Verification environment, annotated verification plans, and even makefiles for running with the various simulators. ARV-Formal uses the same input formats as ARV-Sim and generates properties and assertions based on the specification which can be proved by a formal engine like Mentor Questa® Formal. Recently we partnered with OneSpin to OEM their tool at a price point that will make sense for people who want formal proof for the register verification.

Winners of the giveaways at DAC

Tony Zhang from Intel won the wireless headset and Jack Randall from Altera won the GoPro Hero video camera.

Agnisys mentioned in Cliff Cummings Verification Trip Report on DeepChip

This excerpt is from Cliff Cummings DeepChip 52DAC Trip Report:

    ----    ----    ----    ----    ----    ----   ----

Agnisys IDesignSpec

I have watched this company for the past two years.  Agnisys has a product
called IDesignSpec that helps generate UVM testbench code and in particular,
it seems to have a nice frontend for generating UVM Register code.

The tool also helps traverse through UVM base classes, which is quite useful
for debugging.  IDesignSpec had some more features that I will not expound
in this quick review.  For UVM users who are looking for another tool to
help do UVM development and debug, it is worth a look.

    ----    ----    ----    ----    ----    ----   ----

Thank you Cliff for your kind words.

Overall the show was exciting, we have already started preparing for the next DAC in Austin in 2016, where it will be difficult to miss the Agnisys booth. Look out for it!

The following is an interview of me by EDACafe.  It covers our experience at DAC and how motivated visitors were about our new ARV-Sim and ARV-Formal product offerings.



Semiconductor register verification automation

ic designer's guide to automating design through implementation of semiconductors