IDesignSpec™ – Create Executable Design Code From The Specification – UVM Register Generator
IDesignSpec™ is an award winning product that helps IP/SoC design architects & engineers to create simple yet powerful specification in MS Word, Excel, Libre Office or plain text. The specification is content aware and any conflict in address is checked and highlighted in the specification itself. Any change done in the specification automatically gets translated into code.
IDesignSpec (IDS) captures simple as well as special registers, signals, interrupts, sequences, and generates synthesizable RTL code and interfaces for ARM AMBA® buses like AXI, AHB, APB, AHB3Lite. IDS provides the C/C++ header files and firmware files and enable SW team to develop device driver at an early stage of the design cycle.
IDesignSpec generates a UVM based register model that covers all verification elements like covergroups, coverpoints, coverbins and illegal bins. User can also specify arbitrary hierarchical paths for blocks, register files, registers, register array and memories. Constraint expressions are translated into cover-groups and cover-points, creating bins based on the expressions specified to achieve coverage driven verification. It is also possible to generate the user-defined coverage code and also control the covergroups included in the coverage of that element in the auto-generated register or block UVM Register Model classes.
The generated RTL supports special registers. Here is a list of some of list of supported special registers -
Shadow Register, RO-WO pair at same address, Aliased Register, Locked Register, Trigger-Buffer Register (Wide register), Indirect Register, Interrupt Fields/Registers, Counters, FIFO Register, Paged Register, External (User Defined) Register.
IDesignSpec Key Features – Automate SoC, ASIC and FPGA Specification to Code Generation
- Easy to use Plugin for popular Editors ensures a very rapid adoption rate
- Powerful code generation keeps your specification synchronized with product development:
- System Verilog, Verilog, VHDL Synthesizable design code for industry standard bus protocols (AMBA-AHB, AVALON, and Proprietarybuses)
- SystemC, SystemVerilog based Verification code – UVM Register Generator (based on UVM, OVM and VMM methodology)
- C header files, and C++ Class files for Firmware and Device Drivers
- HTML and PDF documentation
- IP-XACT output
- SystemRDL standard output
- Imports : IP-XACT, SystemRDL, XML, CSV
- Register data stored in native editor format. Provides complete register data portability with design teams and customers
- Extensible: User defined transformations using Tcl or XSLT
IDesignSpec Key Benefits – Improves Design Team Performance
- Automatically verify all addressable registers in the design to ensure generated register code is correct
- Create synthesizable code for registers for design teams and keep them synchronized with requirements
- Faster and more accurate Device Driver, Firmware and application software development eliminates errors in communication of interfaces between functional teams
- Automatically create product documentation for customers and technical publications
- Improves productivity of engineers and quality of results
- Supports Architecture, Design, Verification, Diagnostics, Firmware, Application Software and Documentation teams
IDesignSpec is available as s a plug-in for popular editors that are commonly used to document registers (Microsoft Word, Microsoft Excel) and as a command line utility for Windows, Linux and Solaris platforms.
IDesignSpec has three licensing options, Node Locked, Floating Network License and WAN licensing.