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ARV™ – Automatic Register Verification – Simulation – Formal Verification

The Register Verification Challenge:
Register verification is a significant part of the design verification problem.  It is one of the first aspects of the design that must be tested because the rest of the semiconductor functionality depends on the accuracy of the register implementation.  That is because registers contain the configuration setting of the hardware and is the basis of the hardware / software interface.
ARV helps to auto generate UVM test-bench –bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences helps user to complete the verification right at first time. This verification plan allows easy back-annotation from the test results –thus allowing you track the progress of your verification efforts.

ARV™ – Automatic Register Verification – Simulation – Formal Verification Diagram

ARV automatically generates UVM_sequences for their advanced verification and try to cover all possible input scenarios and generates an effective verification Report in HTML format. This report consist a register verification Plan, which shows the complete summery of the register verification along with their functional coverage and test status corresponding to the register component. The Report also shows all of the register elements along with the corresponding metric groups shows the overall coverage for that element and relative test details which has been passed or fail.
ARV helps to auto verify the special registers like Lock Register, Indirect Register, Constraints Registers and All Register Accesses etc. See in the above ARV coverage report: which shows all of the contents summery in a tabular form, specifies the register model summery, their overall coverage and number of test used along with the status.

Lock register:
The software write access of a register can be locked based on the value of another register field or based on an expression consisting of different registers or fields. See the logical view of Lock Register:

ARV™

Indirect register:
Some registers are not directly accessible via a dedicated address. Indirect access of an array of such registers is accomplished by first writing an “index” register with a value that specifies the array’s offset, followed by a read or write of a “data” register to obtain or set the value for the register at that specified offset. See the logical view of Indirect register with ARV:

ARV™ – Automatic Register Verification – Simulation

ARV automatically generates all of the call back classes into register model, also generates UVM sequences for special registers like Shadow Register, RO-WO pair at same address, Aliased Register, Locked Register, Trigger-Buffer Register (Wide register), Indirect Register,Interrupt Fields/Registers, Counters, FIFO Register, Paged Register, External (User Defined) Registers.

ARV™ – Automatic Register Verification – Simulation – Formal Verification

ARV comes in two configurations, ARV-Formal™ and ARV-Sim™:
ARV-Formal™ is a complete solution that takes the register specification and RTL design as input and performs formal proof to ensure all register operations conform to the specification.  ARV-Formal is powered by an embedded version of (OneSpin 360® DV Verify) to provide a one-button seamless process flow leveraging the power of modern formal verification tools.  ARV-Formal automatically generates assertions directly from the specification therefore completely automating setup and ensuring a very rapid return on investment. Users are using the ARV Formal output with Mentor Questa® Formal.

ARV-Sim™ is a complete register verification solution that integrates with Synopsys VCS®, Cadence Incisive® and Mentor Questa® simulators.  ARV-Sim automatically generates the complete package including bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences required for System Verilog (SV), Universal Verification Methodology (UVM) testing.  It creates the simulator make-files to completely automate the verification process.  This approach eliminates the lengthy and error prone UVM test bench and sequence creation process.  ARV-Sim provides the positive and negative sequences automatically – not just the test bench but also the actual test sequences that stimulates the hardware to ensure that the implementation is correct.
ARV ensures the register implementation is correct:

  • ARV ensures that the coverage metrics are achieved.  The only way we know we have tested all scenarios, is by the coverage.  ARV provides the coverage metrics and writes tests to enable 100% coverage on the registers.
  • ARV supports testing of special registers, for example, lock registers, shadow registers, register aliases, interrupts etc.  It generates sequences for these special registers.
  • Automatically creates register-focused coverage reports.
  • ARV doesn’t need a test bench to start testing the register implementation.
  • User can check either the IDesignSpec generated RTL code, the user’s own implementation, or a mix of the two with standard buses or user defined buses and transactions.
  • Being an add-on to IDesignSpec, it can import IP-XACT, SystemRDL, RALF, Word, Excel, CSV, XML and host of other formats.

ARV-Sim™, ARV-Formal™ Availability:
ARV-Formal™ and ARV-Sim™ are add-on products to IDesignSpec. Engineering teams may request an ARV-Formal™or ARV-Sim™ evaluation by completing this website form.  Also available is a detailed product datasheet and whitepaper.
ARV-Sim™ and ARV-Formal™ are immediately available on Windows and Linux (Redhat and Ubuntu).

Learn the benefits of working with Agnisys

Resources:

Get the Automatic Register Verification Data Sheet

Schedule a Automatic Register Verification Demonstration

how to automate a complete register verification environment

20 Advantages for automating your ASIC or FPGA Transition from Specification to DesignWatch a automatic register verification demonstration video

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