Effective Smart Solutions for Standards-Compliant SoC and IP Verification and Development
In the realm of semiconductor development, often characterized by its pioneers, cowboys, shootouts, gamblers, and gunslingers, one might be tempted to draw a parallel with the historic “Wild West.” However, despite the field’s constant push towards the cutting edge of technology, driving dramatic advances across diverse applications like communications, computing, healthcare, and transportation, it’s crucial to understand that semiconductor development is not akin to the lawless days of the Wild West. Even the most innovative architects and designers, the “pioneers” of our modern age, operate within certain industry boundaries. These boundaries can be defined by technical constraints or business imperatives, but many of them are imposed or necessitated by standards. As an integrated circuit (IC) developer, you are tasked with navigating a complex landscape of standards, encompassing everything from ensuring System-on-Chip or SoC validation and IP SoC verification for interoperability with other chips to meeting the expectations of your discerning end customers.
Many Dimensions of Standards
I have in mind quite a broad definition of standards. People sometimes say “formal standards” when referring to those produced by standardization bodies such as IEEE, ISO, IEC, ANSI, JEDEC, and Accellera. These organizations have a well-defined process to develop and approve standards covering all aspects of electrical and computer engineering, and beyond into the general industry. There are also many associations focused on specific standards, including HTML, PCI, USB, and the RISC-V processor instruction set architecture (ISA).
We often hear the term “de facto standards” to describe widely adopted technologies that are either controlled by no one or are owned by individual companies rather than industry groups. The Intel x86 and ARM processor ISAs, Adobe PDF, and Microsoft Office file formats are common examples. Whatever the source, you need to know the standards required for your target product and ensure that any IP you integrate into your IC, and any EDA tools you use, comply with the relevant specifications.
Support for Design Standards
At Agnisys, our commitment to supporting design standards is unwavering, and we continually strive to align our specification automation solutions with the latest standards, such as the recently introduced SystemRDL 2.0. This dedication is evident right from the core of our offering, beginning with the file formats we endorse for the comprehensive description of your designs, be it registers, memories, or other vital components.
Our IDesignSpec Suite is not only SystemRDL compiler compliant but also seamlessly integrates the IP-XACT standard, ensuring that our solutions meet the highest IP XACT quality requirements, thus facilitating a smoother and more standardized design process. We accept a wide range of file formats, including SystemRDL, IP-XACT, YAML, JSON, RALF, and CSV. This versatility empowers you to effortlessly specify your designs or leverage pre-existing commercial IP blocks with confidence.
Our platform extends its support to conventional tools, such as Microsoft Word, Microsoft Excel, OpenOffice Calc, and intuitive graphical editors, allowing you to define your designs with ease. From these specifications, we generate RTL designs adhering to standard Verilog, VHDL, or SystemC, in line with established industry practices. This adherence to recognized standards is not only a testament to our commitment to quality but also ensures compatibility and interoperability with various design and verification tools in your ecosystem.
Our RTL bus interfaces, another critical aspect of your design, are meticulously crafted to align with respected standards, including APB, AHB, AHB-Lite, AXI-Lite, AXI4, TileLink, Avalon, and Wishbone. This adherence streamlines the interconnection of blocks within your chip using standard system and peripheral buses, while also facilitating connectivity to other devices, particularly when your ASIC involves external ports operating under the same protocols.
Furthermore, our IDS-IPGen solution extends support for essential IP blocks widely used in semiconductor design. This comprehensive library encompasses AES, DMA, GPIO, I2C, I2S, PIC, PWM, SPU, Timer, and UART, all meticulously configured to adhere to either formal or de facto standards, reinforcing their quality and compatibility.
These IP blocks are engineered to be not only conformant but highly flexible and customizable, ensuring a seamless fit into your specific IC requirements. Moreover, our solutions suite extends the flexibility to your hands, empowering you to customize various aspects using standard scripting languages like Tcl, Python, and Velocity.
In the dynamic realm of semiconductor design, adherence to standards and quality is not just a practice; it’s an assurance of a robust and streamlined design process. At Agnisys, our unswerving dedication to SystemRDL compiler, IP-XACT standards, and maintaining IP XACT quality underscores our commitment to facilitating your journey towards excellence in SoC and IP development.
Support beyond Design Standards
Beyond design standards, our commitment to support extends to various facets of the semiconductor development process. In addition to generating RTL code, our solutions encompass an array of critical components that play a pivotal role in design verification and validation, all while maintaining alignment with evolving industry standards, including SystemRDL 2.0 and IP XACT Quality.
For design verification, we go beyond the conventional by generating comprehensive models, sequences, and fully compliant testbenches in standard SystemVerilog, ensuring seamless integration with the Universal Verification Methodology (UVM). This extends the power of your verification environment and facilitates rigorous testing of your designs. But that’s not all – our platform’s versatility extends to C/C++ code generation, producing headers and sequences that seamlessly run on processor models in simulation, aligning with IP-XACT standard. This dynamic capability facilitates crucial hardware/software co-verification and pre-silicon validation, offering a holistic view of design performance.
When it comes to final system validation in your bring-up lab, we appreciate the unique requirements of this phase. In such a lab environment, traditional testbenches may not be available, but our generated C/C++ code is fully compatible with embedded processors in your actual chip. This versatility enables real-world validation, ensuring that your design meets the standards and performs as expected under practical conditions.
Moreover, our generated code is not limited to validation alone. Many programmers harness its power to develop drivers and software that directly interact with your hardware registers. These drivers are versatile, and capable of execution in simulation environments or on host systems connected to your chip during the bring-up phase, ensuring comprehensive coverage in software development and validation.
In the world of semiconductor design, documentation is a cornerstone of every development phase. Our tools are engineered to automate documentation generation in standard HTML, PDF, Markdown, and DITA formats, ensuring complete, up-to-date documentation derived directly from your design specifications. This streamlined documentation process guarantees that every specification change triggers a seamless regeneration of documentation, C/C++ code, verification components, and RTL designs with a simple push of a button. We call this “correct by construction,” where your entire development flow stays synchronized and compliant with the latest standards.
Functional safety, a paramount concern for designs in safety-critical applications, has been in the spotlight with the emergence of advanced driver assistance features and self-driving cars. To meet the stringent requirements of functional safety standards like ISO 26262, our platform generates functional safety mechanisms, further reinforcing the quality and compliance of your designs.
An additional aspect of our commitment to standards support pertains to the development process itself. Our entire IDesignSpec Suite is certified by TÜV SÜD, a globally recognized testing and inspection organization, for meeting the tool qualification criteria of ISO 26262 and the underlying industry-standard IEC 61508. This certification alleviates the need for conducting extensive tool compliance analysis, streamlining the compliance process and ensuring the reliability and safety of your designs.
Conclusion
In summary, our solutions go beyond design standards, embracing the complexity and multifaceted nature of semiconductor development. From validation and software development to functional safety and compliance, our platform is a comprehensive companion that ensures your designs meet the highest standards and expectations in the industry, including SystemRDL compiler and IP XACT Quality.
There are multiple causes for design errors, but some of the most common are related to the design specifications and how they are distributed and maintained throughout the product development lifecycle. Learn how to address this issue by reading The IC Designer’s Guide to Automated Specification of Design and Verification, for Better Products.
