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2015 Year End review – DV Challenges

Wow what a marvelous year 2015 has been to Agnisys, with full of events at the various technical exhibitions, new customers, new features and new products and not to forget – new partnership. It would be unfair to say which event drew the most interest, as we had a number of great visitors at all the events.

Our first marker in 2015 was at DVCon at San Joseon March 2-5 2015, followed by SNUG on March 23-24 in Santa Clara. It was a pleasure to explain the visitors about IDesignSpec features and understanding their requirements and challenges.

EDA companies work hard throughout the year for the DAC preparation to come up with new methodology for the design & verification community. We did the same and announced the Automatic Register Verification (ARV™) at DAC 2015. ARV-Sim helps designer to completely automate the UVM verification process reaching faster coverage closure. ARV-formal takes register specification and RTL design as input and performs a formal proof to ensure all register operations conform to the specification.

During the same time period our partnership flourished with Mentor Graphics and Original Equipment Manufacturer (OEM) with OneSpin Solutions for 360 LaunchPad™. This helped our customers to get the formally verified code from IDesignSpec.

Last but not the least, the ARM TechCon 2015 Nov 10-12, at Santa Clara, was our first experience with the ARM based design verification community. We felt that visitors at ARM TechCon were different from the DVCon and DAC, but they too had similar issues.

Agnisys also sponsored DVConnect Networking Reception at DVCon Europe 2015.
Meeting all the visitors and customers gave us a good understanding of the challenges faced by the industry today. Here are a few that remain a bottleneck in 2015.
– Achieving the functional coverage closure is still tedious for the SoC designs.
– Even though UVM has become the de-facto standard for the verification, still it poses challenges. Creating the register model is a start, the journey to coverage closure starts after that.
– SoC verification and vertical reuse is still a challenge
– Test and Sequence portability continues to be a challenge.

For sure, we are working hard to solve these challenges with our suite of products. We are getting ready for the new events and product announcements in 2016 that will tackle these challenges.

At the end we will like to express our gratitude to customers and partners who helped us in promoting our tools, especially IDesignSpec and DVinsight.

Here is wishing you a Happy New Year 2016 from the entire Agnisys team!!

ic designer's guide to automating design through implementation of semiconductors