Streamlining FPGA Design from Specification to Bitstream
Hardware is verified using simulators. Software compiled and debugged using compilers and debuggers. When it comes to the hardware/software interface, it’s not so straightforward. The FPGA development process can be fragmented in this first phase of design specification.
Take the ARM AMBA® AXI4LITE bus, for example, the most popular bus for interchip communication in Xilinx devices. Hardware designs with configuration and status registers addressable by the AXI4LITE register bus are common. Typically, a user manually creates registers in register transfer level (RTL) code, verifies them using the Universal Verification Methodology (UVM), and generates other artifacts and code fragments for firmware.
Yes, RTL code can be produced automatically using a register generation tool, though integration with the rest of the application logic would need to be done and done manually, as would any specification changes. The Vivado Design Suite interface offers an answer to the integration process, though files would need to be generated so that the integration would be possible without any glitches.
Another promising solution would be to use a correct-by-construction approach. In this scenario, a specification-driven FPGA design flow combining a tool to generate executable design code with Vivado offers a means to create a design specification with information that flows uninterrupted to the bitstream.
The design specification tool captures the hardware specification to enable an architect or system designer to capture hardware/software specifications in any format, including Word, Excel, SystemRDL, IPXACT, RALF or CSV. It generates all possible outputs, such as Verilog, VHDL, SystemVerilog, SystemC, UVM, C headers, SystemRDL, IPXACT, HTML and datasheets without data re-entry or duplication. It can be used to create a variety of outputs and can import various inputs as well.
Because information flows from one system to the other, an integrated design flow is devoid of duplicate data entry. The basic linkage is through Verilog files generated by the design specification tool and imported into Vivado. IP-XACT created by the design specification tool has register, pin and parameter information, while Vivado-generated files have constructs that enable it to work inside the Vivado system.
To create a register specification in a format for the design specification tool, a user would generate Verilog RTL code and a Vivado TCL application programming interface- (API) supported script. He or she would start the project in Vivado, source the generated script (ids_vivado.tcl) to automatically add sources, compile the design, and create and package the IP with AXI interface. The packaged IP would go into the user’s IP repository for integration with Xilinx IP, and the generated RTL code could be connected to the rest of the design.
As for the AMBA® AXI4LITE bus example, the design specification tool would generate RTL code for the AXI client IP for the bus with a configuration setting. The generated client has an AXI bus interface on one end and hardware interface signals on the other, replacing the GPIO block. The tool can produce a TCL script to add the AXI client IP to Vivado.
From there, the user would create a new project in Vivado targeting the Zedboard and a new design in the project where the AXI client IP would be used. The user then would add the AXI client IP to the Viivado IP catalog using the TCL script. The Repository Manager would point the way to the AXI client IP and the added repository would be available from the IP Catalog.
The FPGA development process doesn’t need to be fragmented or a manual effort. The specification-driven flow using IDesignSpec, design specification software from Agnisys, and Vivado is a way to streamline the design specification and the bitstream process.