Register Generation is a Must-Have Capability
Today’s SoC designs contain several thousands of registers and memory map elements. The design team must, from the architecture, create the register and memory map documentation and then map each element to the design code and design verification code for every register and memory map element. To compound this challenge, each bit and its property involve significant time and complexity to ensure the coding is correct.
Registers and memory elements constitute a significant percentage of today’s complex SoC designs. On-chip registers define the software interface to the semiconductor and usually represent the largest portion of the device specification and programmer’s guide. The number of registers continues to increase as SoC design complexity grows, escalating the number of registers compounding documentation, implementation, and maintenance challenges. What’s more, changing specifications during the design cycle necessitates repeated updates to design, test-bench, and register/memory test cases and documentation.
This process repeats itself many times throughout the project. Bugs are only one source of change though. Requests for changes can arise at any design stage, necessitating specification adjustments and updates to downstream code for synchronization.
Manual methods for register generation create multiple sources of error
Register definition starts with an architect scoping out a specification. Armed with a completed specification, the hardware engineer, software engineer, and verification engineers can begin coding each of their different views of the registers described in the functional specification. Once the initial design is in place, verification and software engineers can start running tests. Every time we find a bug, we need to update the specification, and all subsequent outputs must align. Depending on the update's nature, we manually apply the change to all existing design representations. Similarly, problems found at any stage of the development process, have to be fixed in all the design representations. This process relies entirely on good communication between various design teams. These teams are often working in different settings, and most likely are geographically distributed as well. This makes this process tedious and is error-prone with negative project schedule and quality consequences.
What is all too common in these instances of constant change, is due to schedule priorities, the designer may change his code but not update the documentation. Any attempt to manually manage these components impairs productivity and increases the probability of introducing errors in the semiconductor design, embedded software, and design verification process.
The new approach to register generation improves productivity and eliminates errors
By starting from a single source, represented in a high-level register and memory modeling language like SystemRDL, IP-XACT, or for simpler designs, a Word or Excel file, and auto-generating each down-stream representation for documentation, design, and verification, the project complexity decreases and the automation eliminates error sources.
SystemRDL, IP-XACT, Excel, or Word-based specification sources combined with automation provide a single point to make specification changes. From any of these sources, commercial software can drive the automated generation of synthesizable RTL code for the design, C header files for firmware, SV/UVM code for verification, Documentation, and other needed outputs for the project. Although engineers can use SystemRDL, there is an advantage in keeping the register specification close to the remaining hardware design specification. The advantage is obvious – everything about the hardware is in one place.
The bottom line for register generation
The unified register and memory map environment offered by automated tools significantly improve the efficiency of all development teams, especially when they have to react to a specification change. Automation eliminates the risk of inconsistency between environments, ensuring seamless matching and dependency. This approach drastically increases the overall quality of the product and eliminates schedule delays.
