Tales from the DVCon 2016 – Portable Stimulus Resonated
The DVCon Conference this year, was quite eventful for us with a lots of visitors at our booth. We were excited about the interest shown for IDesignSpec™ and our new product ISequenceSpec™ (ISS) – “Portable Sequence Generator for Verification, Firmware & Validation”. It enables users to describe the initialization, config and test sequences and generate UVM, firmware sequences ready to use from an early design stage to post silicon debug.
The message at DVCon was loud and clear … If you are tired of describing the registers and sequences in design, verification, software, validation, ATE, our tools will help save you time and improve quality by providing a common specification driven flow.
This year most of the topics were focused around the UVM, Low Power Verification, Portable stimulus, and spec driven register & sequences generation etc. Agnisys is already leading the space of spec driven Design & Verification artifacts, and working successfully with more than 35 leading semiconductor companies for about a decade. The latest product ISS was built on a strong legacy of IDesignSpec which enables users to create executable design code from the specification & a register model (which could be specified in any format IP-XACT, SystemRDL, etc.). ISS provides a simple specification format to describe the custom sequences and generate the codes that ensure synchronization between various stages from verification to validation.
We hope to continue the fascinating journey of specification driven flow and solve major Design & Verification challenges.
Thank you all for agreeing with our vision, appreciating our products and discussing your challenges with us.