Modern system-on-chip (SoC) devices get more and more complicated each and every day. As the size and complexity of modern electronic semiconductor devices increases, design engineers look for every possible way to reduce manual effort and shrink development time. Specification automation that generates design files directly from executable specifications is one of the best solutions available today.
Every SoC contains a multitude of registers, many of which are part of the hardware-software interface (HSI) through which drivers and embedded code control and monitor the design. Traditionally, designers have implemented their registers by hand-writing register-transfer-level (RTL) code in Verilog, SystemVerilog, VHDL, or SystemC. All hand-coded designs run the risk of typographical errors and other types of mistakes, but register implementation code is especially prone to problems.
This is because register RTL is rather repetitive, with long lists of registers, often with very similar names, and many fields within these registers. Copy-and-paste errors are almost guaranteed to occur, and design reviews don’t always catch the issues. Registers are usually defined in huge spreadsheets that describe every register group, register, field, and register type (read/write, read only, shadow, etc.) Manually translating a textual specification into RTL code is inherently tedious and risky.
Fortunately, specification automation works exceptionally well for registers. In fact, register automation was one of the earliest uses of RTL generation technology. Designers quickly realized that it is much easier and faster to create an executable specification and let a generation tool do the work of writing the RTL. Many formats are available to specify UVM register and memory maps, including the familiar spreadsheets for those who wish to continue using them,
Register definitions change many times over the course of the SoC project, and manually updating the RTL adds even more time and risk. Automation tools can simply regenerate the design every time the executable specification changes. Thus, the designers and the entire development team experience the benefits of an automated approach repeatedly. These benefits are summarized in the following section.
By adopting an automatic code generation tool for executable specifications of registers and memory maps, SoC development teams gain significant productivity benefits, reduce the risk in complex designs, and remove multiple error sources arising from design specifications changes. Every team on the project benefits: design, DV, embedded programming, validation, and documentation. As the industry leader in specification automation, the Agnisys IDesignSpec Suite provides an unparalleled solution to eliminate manual register implementation and greatly reduce the verification and validation efforts as well.