Six Smart Ways Specification Automation Reduces Register Implementation Time
Modern system-on-chip (SoC) devices get more and more complicated each and every day. As the size and complexity of modern electronic semiconductor devices increases, design engineers look for every possible way to reduce manual effort and shrink development time. Specification automation that generates design files directly from executable specifications is one of the best solutions available today.
Fundamental Necessity: Register Design
Every SoC contains a multitude of registers, many of which are part of the hardware-software interface (HSI) through which drivers and embedded code control and monitor the design. Traditionally, designers have implemented their registers by hand-writing register-transfer-level (RTL) code in Verilog, SystemVerilog, VHDL, or SystemC. All hand-coded designs run the risk of typographical errors and other types of mistakes, but register implementation code is especially prone to problems.
This is because register RTL is rather repetitive, with long lists of registers, often with very similar names, and many fields within these registers. Copy-and-paste errors are almost guaranteed to occur, and design reviews don’t always catch the issues. Registers are usually defined in huge spreadsheets that describe every register group, register, field, and register type (read/write, read only, shadow, etc.) Manually translating a textual specification into RTL code is inherently tedious and risky.
The Apt Solution: Automation
Fortunately, specification automation works exceptionally well for registers. In fact, register automation was one of the earliest uses of RTL generation technology. Designers quickly realized that it is much easier and faster to create an executable specification and let a generation tool do the work of writing the RTL. Many formats are available to specify UVM register and memory maps, including the familiar spreadsheets for those who wish to continue using them,
Register definitions change many times over the course of the SoC project, and manually updating the RTL adds even more time and risk. Automation tools can simply regenerate the design every time the executable specification changes. Thus, the designers and the entire development team experience the benefits of an automated approach repeatedly. These benefits are summarized in the following section.
The Six Smart Ways
The automation tools start with a simple input format specification created by the SoC architects or senior design engineers. The tools take that specification and leverage it to provide multiple teams with functionally correct, synthesizable RTL code, UVM verification code, C/C++ header files, C/C++ sequences, and documentation.
This approach benefits not just the designers, but also the design verification (DV) team, who are always under pressure. As the register specification is completed, the DV team uses the code generated to accelerate creation of the UVM register abstraction model, a testbench framework, and sequences to access the registers. This provides the team with an instantly available up-to-date RTL model and testbench-related code. The DV engineers avoid working with design code that is out of date or discovering late in the project that changes in the RTL were not reflected in the testbench, resulting in design bugs due to incomplete tests.
These tools can also generate C/C++ code that accesses the registers while running in the SoC’s embedded processors. This is essential for hardware-software co-verification (pre-silicon validation) as well as post-silicon validation in the bring up lab. This C/C++ code also helps the project programmers develop production drivers, firmware, and embedded software.
The automation tools provide functionality not available in old or technology-specific formats such as SystemRDL, IP-XACT, or simple spreadsheet methods. From the specification, the tools produce complete and robust code for each project Additionally, the tools are configurable to enable the customization of target outputs that may be specific to a project or company.
These tools enable fast turnaround times, allowing multiple iterations per day. Issues discovered during design verification that require specification changes commonly drive these iterations. The consequences of the resulting specification change are immediately propagated to each group on the project.
Because these tools are tested against many designs from many companies, the resulting code that is generated is both syntactically and semantically correct. This eliminates yet another error source for design, verification, and firmware teams.
Agnisys: The Perfect Solution for Tedious Manual Implementation
By adopting an automatic code generation tool for executable specifications of registers and memory maps, SoC development teams gain significant productivity benefits, reduce the risk in complex designs, and remove multiple error sources arising from design specifications changes. Every team on the project benefits: design, DV, embedded programming, validation, and documentation. As the industry leader in specification automation, the Agnisys IDesignSpec Suite provides an unparalleled solution to eliminate manual register implementation and greatly reduce the verification and validation efforts as well.