Prerequisites
To get started with IDS-Validate you need to put 3 things in place.
1. RISC-V gcc tool chain
Setup procedure : riscv/riscv-gnu-toolchain: GNU toolchain for RISC-V, including GCC
Steps to install RISC-V Toolchain are updated in README.md of Git repository and step up in your server.
2. RTL for the RISC-V (Veer from Chips Alliance)
Link: https://github.com/chipsalliance/Cores-VeeR-EH1.git
Chips Alliance has published a register-transfer level (RTL) design abstraction of its in-house designed VeeR-EH1 RISC-V core and is available on GitHub.The design is licensed under the Apache 2.0 licence that allows the core to be used with or without modifications.
Set the ‘RV_ROOT’ environment variable to the root of the VeeR directory structure
Example for bash shell: `export RV_ROOT=/path/to/veer`
Example for csh or its derivatives: `setenv RV_ROOT /path/to/veer`
3. UVM home setup
(This is required to run the examples which are downloaded from this site)
These are simple UVM examples designed to test the setup. They are already located in a zipped folder to test the setup.
compilation_command -f compile_<toolname>.f
(example for questasim use : qverilog -f compile_questa.f)
4. Running Simulation
Command line
Idsbatch <input file> -out “verilog arv_metal iss_firmware “ -dir <output dir> -bus apb
A directory “arv_metal” is created in the output directory with all the above files.
Run simulation :
Xcelium: make -f Makefile TEST_NAME=<test folder name> irun
Note:- The current support is for 32 RISC-V toolchain.