IDS NextGen: SoC/IP Specification & Code Gen Tool | Agnisys
I’m yet to meet a person who doesn’t like simplicity in engineering. I do believe that Electronic Design Automation (EDA) products should be designed in an elegant way, with minimum over-reach. They should let the user do their job and yet all the GUI artifacts should be virtually invisible. Our users have been using IDSBatch for text based register specs and IDSWord and IDSExcel for Word and Excel based specs respectively. However, there was a need to further simplify the specification process and have more control over it. Our users also wanted an integrated environment to not just create addressable registers but create them with all their special properties. And not just registers but parameters and sequences as well.
With all that, in mind, we created IDesignSpec – NextGen (IDS-NG). The next generation of Register and Sequence specification tool that provides a one-stop-shop or a single tool that enables users to create every aspect of an executable register, field-parameter and sequence specification.
Addressable Registers are not new, but we were surprised to see the importance of field-parameters. Often the field-parameters come from Matlab. They play an important role in math intensive digital and analog signal processing applications. These applications are not really concerned which register the parameters are located, as long as their format and size is maintained. So they have a different focus than say a control bit in a register. IDS-NG deals with the field-parameters in an elegant way.
The ability to specify sequences close to the registers and field-parameters is important for the engineer who wants complete control and flexibility in design specification. IDS-NG enables users to create register sequences in the same document type or a completely different specification document.
Our aim has been to create a single environment that the user doesn’t have invoke multiple tools and spread out the information. Over the next few months, we will be adding more and more artifacts to the design specification. We probably won’t stop until the entire design specification can be created in an executable form.
