DAC Day 1: Universal Verification Methodology Adoption – Lots of Room to Grow
The first day of the Design Automation Conference for Agnisys was exciting. We experienced a higher traffic flow than Monday during previous years. This picture shows our booth at the DAC conference.
For those of you who are not aware of Agnisys, our company is focused on providing System Verilog and UniversalVerification Methodology Products, Services and Training to semiconductor design and verification engineers. We have been selling SV/UVM related tools and training for years. From this first day at DAC, it was interesting to note that the technology adoption curve for UVM is more gradual than we would have thought. Sometimes when you are immersed in a market and technology, you perceive the market is moving faster than it is. This is why it is important to participate in trade events like DAC. Back to the UVM trends, while many project teams are in various stages of adoption of model generation for UVM, we still find many companies who have not even started that journey. They are not even using UVM.
It is clear that companies who sell UVM based products that there is lots of room to grow!
The second topic at DAC focused on how to manage the complexity of register and memory map generation for advanced SoCs. Some visitors to our booth had the impression that register automation is difficult or requires the engineer to learn a new program language. Others described their problems maintaining home grown script based solutions. Our recommendations were simple, evaluate what is available in the market and get a solution that works for you. While selecting a register automation tool, ensure that it is easy to use, is extensible, can help you modify the outputs.
All existing customers were happy with the ROI and were recommending our products to other design and verification teams.