Efficient Hardware Description: Transforming SystemRDL into Multiple Formats for Seamless Integration
The first and one of the most important steps of ASIC design flow is chip design specification. The specification can be in the form of a register description of a chip or block. The register specification is used for describing the behavior and structure of a system on chip (SoC).This register design specification can be captured in multiple formats including a standard format such as SystemRDL.
SystemRDL is a language for the design and delivery of intellectual property (IP) products used in designs. The semantics of SystemRDL comprehensively address the life cycle of registers, spanning from specification and model generation to design verification, maintenance, and documentation. In this context, registers extend beyond conventional configuration registers, encompassing register arrays and memories as well.
SystemRDL was developed to address challenges associated with describing and managing registers, aiming to streamline the process. Traditionally, in a design environment, the system architect or hardware designer generates a functional specification for the registers. This specification is usually in textual form, lacking formal syntactic or semantic rules. Subsequently, various team members, including software, hardware, and design verification professionals, use this specification. Each team member leverages the specification to create representations of the data in their respective languages, such as Verilog, VHDL, Universal Verification Methodology (UVM), and SystemVerilog, within their specific domains of chip development. Once the engineering team has implemented the design in a hardware description language (HDL) and established structures for design verification, the phases of design verification and software development can commence. The above process of generation of various outputs from a single SystemRDL specification has been automated along with proper checks to catch bugs and errors at an early stage.
Several challenges are encountered in this chip development process such as alterations in marketing requirements that may necessitate modifications to a register's specification, and physical considerations such as area and timing constraints that can prompt changes to the register's specification. This approach presents several difficulties:
The same information is redundantly replicated across various locations by multiple individuals and teams.
Implementing changes and disseminating them to downstream customers is a laborious, time-consuming, and error-prone task.
Documentation updates often get deferred until the latter stages of the development cycle due to the pressing need to prioritize more critical engineering tasks.
Through the application of SystemRDL and a SystemRDL compiler, users can save time and eliminate errors by using a single source of specification and automatically generating any needed downstream views.
A strong SystemRDL compiler is provided by Agnisys for automatic generation of various outputs from SystemRDL as shown above in the diagram.
SystemRDL to register transfer level (RTL) design output can be automatically generated through the SystemRDL parser, which leads to the generation of correct-by-construction code in the form of conversion such as SystemRDL to Verilog, SystemRDL to VHDL, SystemRDL to SystemC, and SystemRDL to SystemVerilog. The RTL generated provides a comprehensive description of registers and memories, encompassing a bus slave and decoding logic tailored to the chosen user-specific bus protocol. It also incorporates any necessary clock-domain-crossing (CDC) synchronization logic. This feature facilitates the seamless integration of the design with the register bus. The supported interfaces comprise APB, AHB, AHB-Lite, AXI4, AXI4-Lite, TileLink, Avalon, Wishbone, and proprietary buses. Special registers such as aliases, interrupts, or counters can also be generated easily in RTL.
The input provided in SystemRDL can also be utilized to generate UVM output. The resulting SystemRDL to UVM RAL comprises register layer classes designed for building a high-level, object-oriented model for memory-mapped registers and memories. The generated UVM register layer defines several base classes that, when appropriately extended, abstract the read/write operations to registers and memories. This abstraction mechanism facilitates the seamless migration of verification environments and tests from block to system levels without requiring any modifications. Additionally, a UVM-based register test sequence library with predefined test cases can be generated to verify the accurate functioning of registers and memories.
The SystemRDL parser also produces a SystemVerilog model that aligns with the UVM standard, making it suitable for integration into a UVM testbench. This significantly reduces the workload for both design and verification teams. Embedded programmers also benefit from the compiler, as it generates SystemRDL to C/C++ headers for memories, registers, and fields. This eliminates the need for laborious manual transcription of specification details into code and minimizes the risk of errors in the process.
Furthermore, for technical writers, the SystemRDL compiler can generate high-quality documentation for registers and memories, suitable for inclusion in user manuals. Users can select from various formats, including SystemRDL to Microsoft Word, SystemRDL to HTML, SystemRDL to IP-XACT, SystemRDL to PDF, Markdown, and DITA.
The automatic generation of all these project files by the SystemRDL compiler proves to be a valuable time and resource-saving measure early in the project lifecycle. Each file generated by the compiler is one less that needs manual coding. The inherent correct-by-construction nature of specification generation eliminates entire categories of bugs, thereby expediting the verification and pre-silicon validation processes. Furthermore, the SystemRDL compiler incorporates numerous syntax checks, annotation checks, and design rules checks to identify potential issues at an early design stage. The system provides a clear and informative display of errors and warnings, supports automatic address calculation, offers flexibility in changing the hierarchy, and allows the expansion of the SystemRDL language scope through user-defined properties (UDPs) for the incorporation of additional features beyond standard specification features. The robust support for documentation and output parameterization at various levels, along with comprehensive design attributes, further enhances the efficiency and flexibility of the SystemRDL language.