With DVCon 2018 just around the corner, this special edition of the Agnisys Newsletter focuses its spotlight on the future. In this issue, you’ll find expertly curated tips and techniques about our products, solution updates, and detailed documentation to improve your designs. We hope they’ll be a helpful aid to your progress.

Be sure to visit us at DVCon 2018 at the DoubleTree Hotel in San Jose, CA from February 26th to March 1st. We’ll be exhibiting in Booth #805. The showcase will present our advanced tools that use state of the art technology to eliminate bugs, shorten design time, and help you meet your goals. You’ll have a chance to find out more about IDesignSpec NextGen, the next generation product for capturing requirement specification for embedded designs and automatically generating code from it.

We hope to see you soon and, in the meantime, hope these articles are useful to you!

– Anupam Bakshi, CEO, Agnisys, Inc.

Parameterized Reg Map

IDS Field Parameter View is useful when your design has a lot of field parameters. This is true for Math intensive data processing applications with many parameters. The word parameter is overloaded, not to be confused with the Verilog Parameter or VHDL generic. Read more

Interrupts in UVM And VIC Generator

An interrupt is a very important feature which provides information about a higher priority task that needs immediate attention, emitted by hardware or software. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing. It has been implemented in not just in RTL but also in UVM. In addition, vectored interrupt controller can now be created in IDS. Read more

Consolidated Writes in ISequenceSpec

The consolidation of writes is a useful technique to reduce the time and number of writes. In Verification and Validation, it is important to reduce the test time. Consolidated writes reduces the test time both in Verification and post-silicon validation. Read more

Counters In UVM

Counters and Timers are indispensable in digital electronics. But how do you model them in UVM? This article dives deeper into the details. Read more

Multiple Regmaps in UVM

IDesignSpec is a tool which supports multiple bus domains of different bus type like AXI, AHB, AMBA etc. A domain has its own address & there is no interaction between the domains. A block on multiple bus domains may have a different address on each of the domains while the registers inside a block can only be one of the domains. For every bus domain, the generated RTL gets a bus with a prefix identifying that domain and a map is generated in UVM. Read more

 

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