A lot is happening at Agnisys this quarter. We are delighted to introduce this DAC Special Edition of the Agnisys Spotlight Newsletter in 2018. In this issue, we review several enhancements in design specification using IDesignSpec.

• Implementation and complete validation of special registers using IDesignSpec™
• Functional Safety incorporated in IDesignSpec™ for the modern Auto-Industry
• Duolog compatible format supported in IDesignSpec™
• System-Verilog-Assertion Decoder Ring

Agnisys now supports complete validation of special registers

Special registers are complex in nature and are designed based on their applications. All the registers are validated for both hardware and software access. Agnisys uses the  Xilinx® platform for analysis, synthesis, and simulation of special registers. For validation of special registers, we use the Xilinx ZedBoard®.  Read More

Functional safety using IDesignSpec for the modern Auto-Industry

Functional Safety is the new buzzword within Electronic Design. From staying up-to-date on the latest standards to managing all the associated data, complying with functional safety requirements has traditionally been a time-consuming, manual effort. Read More

Agnisys now supports Duolog format for IDesignSpec – Create executable design code from the specification

The input format of Duolog is now supported by IDesignSpec with outputs including Verilog, UVM, CHeader, and SystemC. The outputs generated are compatible with both Duolog as well as IDesignSpec formats. We have incorporated multiple special enhancements and new features to support Duolog compatibility and making the output generation 10x faster. Read More

System Verilog Decoder Ring using Machine Learning

An assertion, in the context of a programming language, is a statement that validates assumptions or checks condition in a program. An assertion, for example, helps notify the user if some legal or illegal combination of values of internal program variables have occurred. Read More

By Comments off June 25, 2018