Agnisys at DVCon US 2023 !
Agnisys will be presenting the workshop “Pushbutton Complete IP Generation” on Monday, February 27, 9:00-10:30am. In IP/SoC design development, after capturing the register specification, the designers work on creating a synthesizable hardware application logic layer for their intended design functionality using the addressable hardware registers.
This workshop shows you how to automatically generate the synthesizable application logic layer along with its UVM RAL and AI-based tests, plus IP blocks and interconnecting logic, all from your specifications.
We will also be discussing and demonstrating our specification automation solutions in the Exhibit Hall at Booth 104 on Tuesday, February 28, 1:30-5:00pm and Wednesday, March 1, 1:30-6:30pm.
Please stop by to chat with us and to take our quiz on SoCs and embedded systems. You could win a portable charger or a portable Bluetooth speaker.